Latch duplication in technology schema (vhdl)

Question

Please note, this is a study question.

I have to describe a simple d-latch in vhdl, and then synthesize it. The problem is that it is a "unary" d-latch, and its single input is mapped directly to its outputs (Q and nQ). You can imagine it as a classical async d-latch, where clk signal is always high. This is useless element in logic, and xilinx synthesizer in most cases gives an empty technology schema. But the reason to keep this element is, for example, creating hardware "watermarks", which present on the schema, but don't affect its logic.
I came up with the following code:

entity dLatch is
  port(
    d: in std_logic;
    q: out std_logic);
end dLatch;

architecture dLatch_beh of dLatch is  
  signal o: std_logic;
begin
  latch: process(d)
  begin
    if d = '1' then
      o <= '1';
    elsif d = '0' then
      o <= '0';
    end if;
  end process;

  q <= o;
end;

This code produce the following technology schema

link

But when I try to add nQ out port, I gain duplication of latch

entity dLatch is
  port(
    d: in std_logic;
    q, nq: out std_logic);
end dLatch;

architecture dLatch_beh of dLatch is  
  signal o: std_logic;
begin
  latch: process(d)
  begin
    if d = '1' then
      o <= '1';
    elsif d = '0' then
      o <= '0';
    end if;
  end process;

  q <= o;
  nq <= not o;
end;

Technology schema: link

I don't understand, why I am getting two completely equal latches here. I expected only one additional 'not' gate. So my question is how to avoid the duplication of latches, or maybe some other way to solve this problem. I use Xilinx ISE Web Pack 14.6 for synthesis.

UPD The solution is to set synthesizer's flag -register_duplication to false.

I never worked with Xilinx/FPGA, so I can't give you some answer. But, in my opinion, I think the synthesizer tried to optimized your latency via dupplicate latches to avoid fanout. Why you don't add some constraint about areas optimization? I hope you will have better result! — Khanh N. Dang
"But the reason to keep this element is, for example, creating hardware "watermarks", which present on the schema, but don't affect its logic." Can you explain to me why anyone would want to get a hardware watermark in the first place? — Russell
If it doesn't affect the logic you are going to have to fight various parts of the toolchain to prevent it being simply deleted : synthesi attributes alone aren't enough; the mapper also optimises away what you have convinced the synthesis tool to leave in. (@Russell; I believe the goal is to trace "clones" of a design provably in court) — user_1818839

Russell Russell · Accepted Answer · 2013-11-07T13:23:29

You're not getting any latches at all. You are looking at the Technology view, so it is showing you what Xilinx components it mapped into. You should be looking at RTL view instead first of all.

Secondly, latches are BAD as your professor probably made you aware. He even says in the description that the view will be blank because the tools will not generate a latch for you. They don't exist in the fabric.

Latch duplication in technology schema (vhdl)

2 Answers