Clock generation in top level testbench

Question

The top level of my testbench looks like this:

module top();
    // `timescale 1ns/1ps

    reg_intf intfc(.clk(Clk));
    register_m dut (intfc);
    register_test_m (intfc);

    bit Clk = 0;
    initial 
    forever #1 Clk = ~Clk;
endmodule : top

reg_intf is an interface, register_m is design module, register_test_m is a program (testbench).

I get this compile error:

Net type cannot be used on the left side of this assignment. The offending expression is : Clk Source info: Clk = (~Clk);

I tried using logic, reg and wire for Clk and got the same error.

toolic toolic · Accepted Answer · 2013-10-15T12:46:35

Move the declaration of Clk before its usage:

module top();
    // `timescale 1ns/1ps
    bit Clk = 0;

    reg_intf intfc(.clk(Clk));
    register_m dut (intfc);
    register_test_m (intfc);

    initial 
    forever #1 Clk = ~Clk;
endmodule : top

Unrelated to your problem: you need an instance name for register_test_m module:

register_test_m tb (intfc);

Clock generation in top level testbench

1 Answers