Signal not changing state in iSim

Question

I'm trying to build a simple pulse generator for a CPLD in VHDL. I have a series of simple if statements that should perform certain tasks depending on the input state of a bus connected to the module.

entity pulse_gen is
Port ( CLK : in  STD_LOGIC;
       pulse_sel_in : in  STD_LOGIC_VECTOR (2 downto 0);
       pulse_r : in  STD_LOGIC;
       pulse_s : inout  STD_LOGIC);
end pulse_gen; 

architecture Behavioral of pulse_gen is

signal pulse_sel: std_logic_vector (2 downto 0);
signal pulse_count: integer;
signal pulse_length: integer range 0 to 100;
signal pulse_a: std_logic;

begin

pulse_sel <= pulse_sel_in;

pulse: process(CLK) is
begin
    if(pulse_sel > "000" and pulse_a = '0') then
        pulse_s <= '1';
        pulse_a <= '1';
    end if;

    if(pulse_a = '1' and pulse_count < pulse_length) then
        pulse_count <= pulse_count + 1;
    end if;

    if(pulse_a = '1' and pulse_count = pulse_length) then
        pulse_s <= '0';
        pulse_a <= '0';
        pulse_count <= 0;
    end if;
end process;

set_max: process(CLK) is
begin
if (CLK'event) then
    case pulse_sel is
        when "001" => pulse_length <= 1;
        when "010" => pulse_length <= 10;
        when "011" => pulse_length <= 100;
        when others => null;
    end case;
end if;
end process;

end Behavioral;

When running this module in iSim, forcing the _pulse_s_ bus to anything but 000 should trigger the first if statement in the pulse process, which it does. However, in the simulation, the _pulse_a_ signal is never set to logic high. Now I have spent hours writing this module in different ways, but I have absolutely no idea why this doesn't happen. I'm relatively new to VHDL, so I wonder if there's some kind of syntax or procedural error that I'm just completely missing. Any ideas?

have you tried everything in process pulse inside if rising_edge(CLK)? you haven't used CLK in that process. — Thanushan
Thanks, I've just tried this now and it still makes no difference. On forcing the pulse_sel_in input to logic high, the pulse_length gets set, and pulse_s goes to logic high, but still no activity for pulse_a. — Dave Moore

Russell Russell · Accepted Answer · 2013-10-14T12:10:50

@Philippe is correct. You need to assign pulse_a to some value, 0 or 1 when you define the signal. Add this: signal pulse_a: std_logic := '0'; and it will work.

You said that you're forcing it low in iSim. Well guess what? When you force it low, it stays low! So your code won't be able to change it!

EDIT: You should also be assigning pulse_count to some initial value.

Signal not changing state in iSim

2 Answers