Verilog Timing Analysis for Fixed inputs

Question

I have a simple piece of Verilog code where i fix two numbers. 45 and 46. Multiply them and show the output. I wrote a simple piece of Verilog code to do that.

However, when I Generate the Post-Synthesis Simulation Model, the Synthesis report does not show any Timing Analysis. However, when the variables are inputs, it finds the logic and routing time for the circuit.

I am interested in these metrics for a circuit created for fixed inputs.

This is my code:

module SimpleMult(
    outProd
     );
    reg signed[7:0] mult1;
    reg signed[7:0] mult2;
   output reg signed[15:0]outProd;
    initial begin
     mult1 = 45;
     mult2 = 46;
    end

    always@(*) begin
    outProd = mult1 * mult2;
    end
endmodule

Is there anyway I can get the timing analysis to work for this?

I think that the best approximation you can get (without analog simulation) may be obtained if you find a way to restrict (during STA) the analyzed values of your inputs (which you should define) to 0,0 and 45,46. Though, I don't know whether STA tools support this functionality. — Vasiliy

Morgan Morgan · Accepted Answer · 2013-06-18T10:03:31

The issue you face here is that the multiplication of constants is a constant and therefore has no timing.

A method to measure the timing would be to synthesise the multiplier with 2 inputs. Then perform a gate level sim including the SDF timing information. Taking both inputs from 0, to the fixed values. In a waveform editor you should be able to see ripple on the output of the multiplier. Measure the time from new input to settled output.

Remembering that Silicon timing is quite variable, You might get fast or slow (or centred) Silicon. Temperature will also effect the timings. You will need to run the sim with at least two corners Max and Min. Resulting in a max and min time to transition from (0 input to) fixed input to stable result.

Also realise that the timing used in this method is from 0, it will be different with different starting conditions.

You could try having two LUTs (Look Up Tables) holding the input values 0 and your fixed ones and see what your synth tool does. Likely will optimise to a LUT with 0 and the answer.

Verilog Timing Analysis for Fixed inputs

2 Answers