Verilog - individual output arrays

Question

This is my first time on stackoverflow.com and new to verilog coding. I may use some terms incorrectly so if I do please correct me so I can be clearer in future posts.

I am using an Altera FPGA board where there are 7 LEDG lights which can be triggered on and off. For my project I am making a BCD adder where LEDG [7] turns on when the BCD value is not 0 - 9. However, I don't want to declare outputs [6:4]. LEDG[3:0] displays the binary equivalent of the summation of the two inputs.

I thought I could use two separate declaration statements but it tells me that LEDG is already declared which it is. I then tried to combine it using brackets but it also complained about that. Is there any way to simplify my code. Below are examples of what I've tried.

Example 1:

module BCD (..., LEDG, ...);
output reg [3:0] LEDG;
output reg [7] LEDG;
endmodule

Example 2:

module BCD (..., LEDG, ...);
output reg ({[3:0], [7]} LEDG);
endmodule

Any help would be greatly appreciated! Thanks in advance. :-)

Answer 1

What you're trying to do is not possible, if you're going to output a bus then you must specify a single contiguous range.

You should just declare an output reg [7:0] if you need to output [7] and [3:0].

You can leave the unused bits undriven, or if that gives a synthesis warning/error then tie them off to 0 or 1 if you don't care about their value (LEDG[6:4] = 3'b0).

Answer 2

module(...NBCD_FLAG, LEDG...);
output reg [3:0] LEDG;
output wire NBCD_FLAG;

In your .qsf file assign LEDG to leds 3-0 on you board and NBED_FLAG to led 7. This way you can use led 6-4 for some other purpose.