makefile interpret variable in a loop

Question

I'm trying to get a variable to be interpreted as another variable in a for loop, and I can't figure out how this should be done. My test is:

TEST= one two three

one := one1
two := two2
three := three3

all:
    @echo $(TEST)
    @for NUM in $(TEST) ; do \
        echo $($$NUM) ; \
    done ; exit 0

foo:
    echo

The end result: I have a number of Makefiles with an include pointing to one central makefile. I'd like for these individual makefiles to contain variables of files to concatinate together - but different directories have different files. So, makefile in ./1/ might be: one := "file0 file1 file2" two := "other0 other1 other2" three := "boo.txt blah.txt" include ../main.mk

and ./2/ might be one := "file0 file5 file6" two := "foo bar baz" three:= "blah.txt" include ../main.mk

Etan Reisner Etan Reisner · Accepted Answer · 2013-02-12T12:57:23

That can't work the way you have it written. You are crossing boundaries.

By the time your shell loop is running the make variables have been expanded already so what your loop body ends up containing is 'echo ;'.

You need to do your loop at the make level if you want to get your intended output.

Something like:

TEST= one two three

one := one1
two := two2
three := three3

define loop
        $(foreach n,$(TEST),@echo $($n)
)
endef

all:
        @echo $(TEST)
        $(loop)

Though I feel like there should be a slightly simpler way I just don't see it at the moment.

makefile interpret variable in a loop

1 Answers