Execution flow of Makefile which includes other makefile

Question

1) How the makefile execution flow works, In case suppose makefile-1 includes another makefile-2 and makefile-2 includes another makefile-3 ?

2) In case if the included makefiles contains some rules and variables that are supposed to be used by all three - how it works ? what happens if one includes the same makefile more than once ?

3) Use of export for variables of included makefile ? - Are they available in all of there makefile,

what is my understanding, The makefile interpreter(or I don't know which term suits better here) reads as line in the makefile, and if there is any include directive it makes all the variable/rules available in the makefile(top level make-which includes other).

4) But what happens if two included makefiles overrides variables or rule of each others ? Is it like the last included makefile takes the priority ?

5) If any rule in the included makefile calls the rule of top level makefile, does it executes top level makefile entirely (starting from the first line) ?

6) there are two kind of assignments in make:

i) expanded at the time of use (=)

ii) expanded at the time of declaration (:=) How this kind of variables handles in multilevel makefiles ?

7) what happens if I use gnumake's functions like notdir, patsubt when I creates a list

File = abc def ghi 
File += $(notdir ghi/jkl)

when does this notdir call happens ?

(and also if I use ':=' what will be the difference ?)

Consider make contains following rule, Does it gets called at the time when dependency is resolved ?

rule : File

Answer 1

Nothing special WRT ordering happens when a makefile is included. To make, it's as if you constructed one big makefile where the contents of the included makefile are inserted where the include statement appears in the parent makefile, then passed the one big makefile to make.

So, the rules for overriding things (variables, etc.) are identical to if you override a variable in a single makefile: each subsequent assignment of the variable replaces the value of the previous assignment.

If you define a (single-colon) rule with a recipe for a target, then do it again later, you get an error message and make ignores one of them.

The first explicit target listed in any makefile, included or not, will be the default target.

Etc.

Remember that make never "executes" any makefile entirely. Make is not a procedural language, like a shell script. It first parses all the makefiles and constructs a dependency graph internally. Then it chooses the default target or targets, and walks the sections of the graph starting with each one.

Edited:

If the above doesn't help you answer your other questions, then I think you should just experiment a little bit. Try it and see what happens! It's easier than asking us to explain it, plus you'll understand it much better if you figure it out yourself.