How can I use a prepared module in a loop in Verilog?

Question

I am trying to generate 128 parellel XOR gates, and then connecting their outputs to 64 XOR gates in Verilog. I use a module that prepared named "EXOR". My problem is: When I put this module "EXOR" into the loop, program gives syntax error "unexpected token: 'EXOR'". And I want to name the gates exor0, exor1, ... .

How can I solve it?

initial begin 
  for (i=0; i<128 ; i=i +1 )
    EXOR exor[i](.I1(m[2*i]), .I2(m[2*i+1]), .o(t[i]));
end

initial begin 
  for (i=0; i<64 ; i=i +1 )
    EXOR exor[i+128](.I1(t[2*i]), .I2(t[2*i+1]), .o(f[i]));
end

initial begin 
  for (i=0; i<32 ; i=i +1 )
    EXOR exor[i+192](.I1(f[2*i]), .I2(f[2*i+1]), .o(g[i]));
end

Generate statements, you can not put instantiations in an initial or always @ block — Morgan
Why create an EXOR module when there is already a native primitive xor? Does this need to be done as gates? It would be easier as behavioral, e.g.: for (i=0; i<128; i=i+1) t[i] = m[2*i] ^ m[2*i+1]; — Greg

Brian Magnuson Brian Magnuson · Accepted Answer · 2012-12-07T13:08:21

To elaborate on Munkymorgy's answer what you're looking for here is a generate loop. 'initial' and 'always' blocks are used for "runtime" constructs. Since you're trying to create an array on instances you want something interpreted at elaboration time.

genvar i;

generate
   for (i = 0; i < 64; i = i + 1) begin : gen_loop
      EXOR exor(.I1(m[2 * i]), .I2(m[2 * i + 1], .o(t[i]));
   end
endgenerate

Two things:

1) The loop variable has to be declared as a 'genvar'

2) The for loop needs to be named. This will be used in the hierarchical name of the instance.

How can I use a prepared module in a loop in Verilog?

1 Answers