Interrupt handling for page faults to service device memory copies in x86

1
votes

I'm trying to work out the control flow of an interrupt, specifically a page fault, on an x86 CPU. Here's what I can figure out so far:

  1. IDT is populated with service routine addresses.
  2. Interrupt occurs.
  3. CPU saves EFLAGS, CS and EIP to stack.
  4. EIP is set to ISR address fetched from IDT, i.e. mov eip, [idtr+interruptNum*4]
  5. Interrupt routine executes.
  6. Interrupt routine completes with an iret instruction.

Now, let's say the interrupt is actually a page fault relating to a NIC buffer. Would the ISR use out to tell the DMA controller to issue a copy from the system memory to the device (or vice versa), or am I way off base here?

1
x86cpuinterruptinterrupt-handlingdma
No, the page fault handler is very distinct from the device driver that handles a NIC. DMA doesn't cause page faults, it uses physical memory in the non-paged pool. – Hans Passant
I didn't mean that the DMA caused page faults, I meant that the ISR would tell the DMA controller to copy a block of memory from the system memory (RAM) to the device. Perhaps my question wasn't quite explanatory enough, I'll make an edit. – Polynomial
Oh, wait, now I get it. So the interrupt handler would be used to signal the device driver, which then does whatever it needs to to communicate with the device. In that case, how is the signalling usually done? I'm under the impression that ISRs are meant to run very quickly, but a device driver might need to do quite a bit of work to communicate with the device. Or would the interrupt line be cleared immediately, so that new interrupts can come through? – Polynomial
Would the downvoter care to explain their vote? – Polynomial
+1 to counter the unjustified downvote - seems like a good Q to me – Basic

1 Answers

2
votes

I believe you're misunderstanding the way memory-mapped I/O works.

When a device uses memory-mapped I/O, it is assigned a physical address range. The northbridge and/or southbridge as appropriate is configured so that when the CPU performs memory operations within that address range, the operations are directed to the device rather than to RAM. There is no copy of the same address space in RAM, and DMA is not involved.

So that the device driver can access the memory-mapped I/O, the operating system will map a virtual address range to the relevant physical address range. Typically, for performance reasons, this will be a global mapping (i.e., the same mapping in every process) with access restricted to kernel mode. Since this virtual address space is always mapped, no page faults occur.

If the device uses DMA rather than memory-mapped I/O, things are a bit different. The device driver will typically have reserved a block of non-pageable memory for the operation, so again, no page faults are involved. This memory does not even have to be mapped into the virtual address space in order to perform a DMA operation, because the DMA controller works with physical rather than virtual addresses. (Of course there will have to be a virtual address space mapping at some stage so that the memory block can be read/written by the device driver.)