Error (10170): Verilog HDL syntax error at Test1.sv(29) near text: “program”; expecting a description

Question

Trying to test a Verilog module via System Verilog. I'm analysing the RTL Simulation and I get the error:

Error (10170): Verilog HDL syntax error at Test1.sv(29) near text: "program"; expecting a description

Can anyone help me out?

I tried debugging it, but no results. It shows the error here after I instantiated the module I want to test.

interface valid_in1 (input clk);
logic din;
logic res;
logic out;

modport dut (input clk, din, res, output out);
modport tb (input out, output clk, din, res);

task monitor ();
while (1) begin
@(posedge clk);

if (din==1'b1) begin
$display ("@%0dns res %b out %b din %b clk %b",
$time, res, out, din, clk);
end
 end
endtask
endinterface: valid_in1

module valid (valid_in1.dut din);

valid_in dut (.clk(din.clk),
              .din(din.din),
              .res(din.res),
              .out(din.out));         
endmodule

program validprog (valid_in1.tb tin);

default clocking cb @(posedge tin.clk);
endclocking

initial begin
fork
tin.monitor();
join_none
tin.res <= 1;
tin.din <= 0;
##10 tin.res <= 0;
##1 tin.din <= 1;
##10 tin.din <= 0;
##5 $finish;
end
endprogram

module Test1 ();
logic clk= 0;
always #1 clk++;

valid_in1 cin (clk);
valid dut (cin);
validprog tb (cin);
endmodule

This is the valid_in module im trying to test out:

 module d_flip(din, clk, res, q, revq);

input din, clk, res;
output q, revq;
reg q;

assign revq = ~q;

always @(clk) begin

if(res == 0)
    q = 0;

else 
    q = din;
end
endmodule

module valid_in(din, clk, res, out);

input din, clk, res;
output out;
wire q1, revq1, q2, revq2;

d_flip bl1(din, clk, res, q1, revq1);
d_flip bl2(q1, clk, res, q2, revq2);
and(out, q1, revq2);

endmodule

program is a system verilog syntax. Did you use a system verilog compilation? There are a few issues in definition of your interface, but no syntax errors. — Serge
Hi ! Yes, it is system verilog compiler. The interface definition didn't showed any errors, nor warnings. — ERM

Serge Serge · Accepted Answer · 2021-02-01T16:35:22

These should work in SV compilation:

task from the interface must be imported in the modport (imported into the module)
your interface has only one port (clk) and cannot be instantiated with multiple ports

interface valid_in1 (input clk);
logic din;
logic res;
logic out;
 
  modport dut (input clk, din, res, output out);
  modport tb (input out,  clk, output din, res, import monitor); // << import task

  task monitor ();
    while (1) begin
      @(posedge clk);

      if (din==1'b1) begin
        $display ("@%0dns res %b out %b din %b clk %b",
                  $time, res, out, din, clk);
      end
    end
  endtask
endinterface: valid_in1


module valid (valid_in1.dut din);
  // I believe that you meant 'valid_in1', not just 'valid_in'.
  // it could have caused your compilation issue. Check other errors and warnings.
  valid_in1 dut (.clk(din.clk) // << only one port can be used (clk)
              /*, .din(din.din),
              .res(din.res),
              .out(din.out)*/);         

endmodule

Other than that, synopsys and mentor in eda playground agree with lrm and compile it. (cadence, as in most cases, has issues).

Error (10170): Verilog HDL syntax error at Test1.sv(29) near text: “program”; expecting a description

1 Answers