Array/STD_LOGIC_VECTOR in VHDL

Question

On my BASYS-3 board I want to use 4 of the switches and output different things depending on the combination of these switches. For example, if switch 12 is turned on I want a value assigned to a signal. I managed to upload my code onto the board but when I flicked through the switches nothing happened on the display.

Below is part of my constraints file for this segment of code:

#Switches
#SW12
set_property -dict { PACKAGE_PIN W2   IOSTANDARD LVCMOS33 } [get_ports {i_SW[0]}]
#SW13
set_property -dict { PACKAGE_PIN U1   IOSTANDARD LVCMOS33 } [get_ports {i_SW[1]}]
#SW14
set_property -dict { PACKAGE_PIN T1   IOSTANDARD LVCMOS33 } [get_ports {i_SW[2]}]
#SW15
set_property -dict { PACKAGE_PIN R2   IOSTANDARD LVCMOS33 } [get_ports {i_SW[3]}]

and this is how I have written it in the port map of my top level entity:

i_SW : in STD_LOGIC_VECTOR (3 downto 0)

to then be called in this fashion in a separate entity:

case i_SW is
    when "1000" => -- data select 0
        --doesn't matter ;
        --doesn't matter ;

This code is supposed to read the switch values and store it in the STD_LOGIC_VECTOR and then read it for the case statement. For example, if SW12 was flicked on I would expect the vector to hold "1000" and so it would go into that case.

I am wondering whether I have written this in the incorrect format and there's a different way to do it? Should I store it in an array and the declare that array in the port map to then use in other entities?

Thank you

EDIT: When I simulate the code it shows me that i_SW is 'U' which I believe means uninitialized but that is probably just a problem with my testbench.

It looks like you are on the right track. Since "nothing happened on the display", first try sending a fixed pattern to the output, see if that works. If it does, then try copying inputs to outputs, and see if they respond when you change inputs. Add your processing only after you know outputs and inputs are all working. — Ben Voigt
Hi Ben, thank you for the reply. I didn't say this as I didn't think it was important but now I'm thinking it may be. When I turned on the board the display showed 0000 which is my final case statement (if others => 0000). Would this change your answer at all? — George
I would still follow the same steps of using extremely simple VHDL first, to verify that your port and pin mappings are working the way that you expect. — Ben Voigt

Simon Richter Simon Richter · Accepted Answer · 2020-12-07T16:34:19

The vector is declared with downto, so the order of elements is 3,2,1,0 and "1000" corresponds to SW15, not SW12.

Also, the switches may be low-active, a lot of development boards are wired like this -- then you'd have to invert the values as well.

Array/STD_LOGIC_VECTOR in VHDL

1 Answers