What fields are there in virtual and physical addresses?

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While studying virtual memory concepts, I understood that a virtual address (generated by a processor to access memory location) contains page number and page offset. we use a page table to get the physical address (frame number essentially) corresponding to this page number.

Now, if these addresses (physical/virtual) operate in terms of pages/frames, how does the processor access a cache which operates in terms of blocks/lines?

Also, if the virtual address consists of only page number and page offset, where does the tag bits come from which is used to check if the cache set (specified by index/set bits) contains the required data or not?

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cachingmemory-managementcpu-architecturememory-addressvirtual-memory
Different uses of the same address can break it up different ways. If you insist on thinking of it like a C data structure with fixed fields, think of it as a union {} of multiple different structs. – Peter Cordes
@PeterCordes Can you explain how same bits can be used for accessing two different addressing schemes? Where exactly is the overlapping between these two types of addresses? Type 1: PageNumber + PageOffset Type2: Tag + Set/Index + Offset – Rajesh
Virtually indexed physically tagged cache Synonym shows an example of a system breaking up addresses in 2 different ways, for paging (page number / page offset) and for cache (tag / index / offset) – Peter Cordes
Or in general for caches, Cache Addressing: Length of Index, Block offset, Byte offset & Tag? . Also How to compute cache bit widths for tags, indices and offsets in a set-associative cache and TLB has a diagram of breaking up and translating a virtual address. – Peter Cordes
@PeterCordes Is it safe to assume that the data transfers between cache and RAM takes place in terms of blocks, and transfers between RAM and disk take place in terms of pages? One more question, when CPU issues a memory access request, what unit of data it tries to operate on? Byte/Word or block or page? I assume it's just trying to access a byte/word. – Rajesh

1 Answers

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I figured out the answer to this question.

  1. Same address can be used/interpreted for accessing two different addressing schemes. (Thanks @PeterCordes for pointing this out)

    • Scheme 1 (To access the TLB): PageNumber + PageOffset
    • Scheme 2 (To access the cache): Tag + Set/Index + Offset

  2. Usually in VIPT caches, the page number comes from higher-order TAG bits, and the page offset comes from lower-order TAG bits along with SET and OFFSET bits. To prevent aliasing (multiple virtual addresses mapping to same physical address), it is important that SET/INDEX bits come fully from page offset. This restriction limits the size of the cache.