How to switch modules in verilog?

Question

I want to use SW[15] to switch between module A_7seg and B_7seg but it does not work. (2 modules work separately)

module mix(input CLOCK,input [15:0]SW,output reg [15:0] led,output [3:0] an,output reg[7:0] seg);
    generate
    case(SW[15])
        1'b0:A_7seg (.CLOCK(CLOCK),.an(an),.seg(seg));
        1'b1:B_7seg (.CLOCK(CLOCK),.SW(SW),.led(led),.an(an),.seg(seg));
    endcase
    endgenerate
endmodule

generate block is used to instantiate modules conditionally at 'compile-time', not 'run-time'. Either you use a parameter to select which module to instantiate, which leads to either A_7seg or B_7seg is present; or you instantiate both (more area consumption), and use a wire to select which one is currently working. — Light

Light Light · Accepted Answer · 2020-09-23T03:21:11

Since '2 modules work separately', the simple way is to use SW[15] to select between 2 modules' outputs.

module mix(
    input CLOCK,
    input [15:0] SW,
    output reg [15:0] led,
    output reg [3:0] an,
    output reg [7:0] seg
);
    wire [15:0] B_led;
    wire [3:0] A_an, B_an;
    wire [7:0] A_seg, B_seg;

    // if not using 'generate' block, modules are instantiated at
    // the top level, not in other 'if'/'case'/... structures.
    // and name the 2 instantiations
    A_7seg u_A_7seg (.CLOCK(CLOCK), .an(A_an), .seg(A_seg));
    B_7seg u_B_7seg (.CLOCK(CLOCK), .SW(SW), .led(B_led), .an(B_an), .seg(B_seg));

    // this extra circuit is needed to select between the two
    always@(*)begin
        if(SW[15])begin
            led = B_led;
            an  = B_an;
            seg = B_seg;
        end
        else begin
            led = 16'h0;  // <-- I assume the inactive value for 'led' is all-zero
            an  = A_an;
            seg = A_seg;
        end
    end
endmodule

You may also want to use SW[15] to gate the inputs to the one that is not currently working to reduce power consumption.

You need to figure out the schematic before you understand how to write the code.

How to switch modules in verilog?

1 Answers