UVM compile fail if “abc_seq_item m_tx;” is not the first executable line in “task run_phase(uvm_phase phase)”

1
votes

I encounter this case a couple of times.

In the user defined uvm driver, if I put like below for the run_phase, it fails.

task run_phase(uvm_phase phase);
    #1; // It fail even if I put something like `uvm_info() instead of "#1".
    abc_seq_item m_tx;
    ...

This similar behavior could also happen in the sequence class.

task body();
    #1;
    abc_seq_item m_tx;
    ...

It will pass if "abc_seq_item m_tx" is the first executable in the task. May I know why exactly is the reason?

1
system-veriloguvm

1 Answers

2
votes

This is a general BNF rule from Verilog that in any procedural block of code, declarations must come before any statements. This rule holds for any task, function, begin/end, fork/join block. I'm not sure if there's a specific place in the LRM that mentions this in words, but its codified in the BNF in you look for block_item_declaration