I have some simplified test structure. The testcase apb_write_verify2y_test calls apb_write_verify2y_seq, then it calls apb_write_seq.
However, m_seq.m_addr=16'h0010 (at apb_write_verify2y_test) does not passed to m_apb_write_seq.m_addr as it should.
If I change the line in apb_write_verify2y_seq like below, then it is working:
assert(m_apb_write_seq.randomize() with {m_apb_write_seq.m_addr == 16'h0010;});
Can you please help me on this?
class apb_write_verify2y_test extends apb_base_test;
`uvm_component_utils(apb_write_verify2y_test)
virtual task run_phase(uvm_phase phase);
apb_write_verify2y_seq m_seq;
phase.raise_objection(.obj(this));
m_seq = apb_write_verify2y_seq::type_id::create(.name("m_seq"));
m_seq.m_addr = 16'h0010;
m_seq.start(m_env.m_apb_agent.m_apb_seqr);
#10ns ;
phase.drop_objection(.obj(this));
endtask: run_phase
class apb_write_verify2y_seq extends uvm_sequence#(apb_seq_item);
`uvm_object_utils(apb_write_verify2y_seq)
logic [15:0] m_addr;
task body();
apb_write_seq m_apb_write_seq;
repeat (2) begin
m_apb_write_seq = apb_write_seq::type_id::create(.name("m_apb_write_seq"));
assert(m_apb_write_seq.randomize() with {m_apb_write_seq.m_addr == m_addr;});
`uvm_info("debug1", $sformatf("m_seq has m_addr=%h, m_apb_write_seq.m_addr=%h", m_addr, m_apb_write_seq.m_addr ), UVM_HIGH);
m_apb_write_seq.start(m_sequencer);
end
endtask: body
class apb_write_seq extends uvm_sequence#(apb_seq_item);
`uvm_object_utils(apb_write_seq)
rand logic [15:0] m_addr;
task body();
apb_seq_item m_apb_seq_item;
m_apb_seq_item = apb_seq_item::type_id::create(.name("m_apb_seq_item"));
start_item(m_apb_seq_item);
assert(m_apb_seq_item.randomize() with { m_apb_seq_item.tr_addr == m_addr;});
finish_item(m_apb_seq_item);
endtask