4-bit synchronous double down counter jk flip flop

Question

Recently, I am trying to learn digital design and Verilog HDL. I am currently working on flip flops. I was trying to construct a 4-bit synchronous double countdown (down counter) with jk flip flop.

Ex: 1111 - 1101 - 1011 - 1001 - .. (15 - 13 - 11 - ..) etc.

While I was researching on the net, I always found synchronous down counter like 1111 - 1110 - 1101 etc.

How can I implement 4-bit synchronous double countdown (down counter) with jk flip flop?

This is clearly a homework assignment. Please edit the question and show your effort. Hint: what do you see if you omit the LSB? — Greg

mcleod_ideafix mcleod_ideafix · Accepted Answer · 2020-06-02T19:53:25

First thing that comes to my mind is a FSM. What buggers me is the requirement of using JK flipflops. Verilog can allow designs at the PMOS/NMOS level, but I'm not sure this is what you really wwant to do.

A behavioral description of such counter is very straightforward if a FSM is implemented. This one is a 3-bit double countdown. I think you can easily modify it to siut your 4-bit counter.

module countdown (
  input wire clk,
  input wire rst,
  output reg [2:0] out
  );

  initial out = 3'd7;

  always @(posedge clk or posedge rst) begin
    if (rst == 1'b1) begin
      out <= 3'd7;
    end
    else begin
      case (out)
        3'd7   : out <= 3'd5;
        3'd5   : out <= 3'd3;
        3'd3   : out <= 3'd1;
        3'd1   : out <= 3'd7;
        default: out <= 3'd7;
      endcase
    end
  end
endmodule

Of course, there is another way: using an adder. For 4 bits, it would be like this:

module countdown4b (
  input wire clk,
  input wire rst,
  output reg [3:0] out
  );

  initial out = 4'b1111;

  always @(posedge clk)
    out <= out + 4'b1110;  // -2

endmodule

4-bit synchronous double down counter jk flip flop

1 Answers