Why does MIPS use 'PC+4' as base address when calculating branch target address?

Question

If you observe the MIPS 5-stage pipeline(1.Instruction Fetch - 2.Instruction Decode - 3.Execute - 4.Memory Access - 5.Writeback), whether to branch or not is finally determined at Execute stage.

MIPS 5-stage pipeline

You can see in the image that the upper output of ALU is fed into a MUX to choose between normal PC step and branch.

Hence, when the CPU decides whether to branch, two pipeline stages have passed from the IF stage of corresponding instruction. Suppose PC1 = PC when IF and PC2 = PC when decides to branch. Hence PC2 = PC1+4. In order to revert PC2 to PC1+4, additional hardware is required. (for operation PC2-4)

In spite of this disadvantage, I wonder why the MIPS processor uses PC+4 as base address rather than using PC+8 as it is.

Answer 1

If anything you'd need more hardware to get PC+8, or it would complicate exception-return handling and stuff even more if you were thinking you could skip the pipeline stages and have the branch offset apply to the value of the fetch-stage address. (MIPS branch delay slots mean that returning from an exception needs a PC and separate next-PC in case the branch delay slot from a taken branch faulted.)

Also what if fetch stalls and doesn't advance PC?

In actual classic MIPS, branch latency is 1 cycle so it makes sense that branches are relative to the instruction in the branch-delay slot not 2 instructions later; How to Calculate Jump Target Address and Branch Target Address?.

Also, the IF stage has already computed PC+4 so it can send that value down the pipeline along with the instruction. You don't want long wires if you can avoid it; it makes sense to send the PC+4 value through the latches between pipeline stages.