2
votes

I am trying to store 64 bits to memory from a V register to an address held in an X register but I get the error, "invalid addressing mode at operand 2 -- `st1 {V1.D}[0],[x20,640]".

From the ARMv8 Instruction Set Overview, the operation should look like this:

ST1 {Vt.<\T>}[index], vaddr Store single 1-element structure from one lane (of one register)

All SIMD load-store structure instructions use the syntax term vaddr as shorthand for the following addressing modes: [base] Memory addressed by base register Xn or SP. [base],Xm Memory addressed by base register Xn or SP, post-incremented by 64-bit index register Xm. [base],#immMemory addressed by Xn or SP, post-incremented by an immediate value which must equal the total number of bytes transferred to/from memory.

Below is the code concretely showing what I am trying to accomplish. To me, it looks like it should be fine.

__asm__ volatile (
   "MOV V0.D[0], %[A_MASK]      \n\t"
   "ST1 {V0.D}[0], %[D]         \n\t"
   :
   : [D] "m" (<pointer>), [A_MASK] "r" (0xFF000000)
   : "memory", "V0"
);
1

1 Answers

4
votes

st1 does not take an offset so [x20,640] is illegal. Only [x20] and similar would be legal. To force gcc to generate a proper address use the Q constraint which the manual defines as

A memory address which uses a single base register with no offset

Note that gcc has vector support so you might not need to use assembly for this.