BT invalid instruction operands

Question

Back with BT, I'm getting: IOfinSICB.asm(248) : error A2070: invalid instruction operands

IOfinSICB.asm(251) : error A2070: invalid instruction operands

IOfinSICB.asm(257) : error A2070: invalid instruction operands

I have 450 bit array which I need to test. I defined it as: TabDeComp Byte 58 Dup (0) From what I've red you can test memory bits displaced by the number held in the register, every 8 is the next byte, very first is 0 to 7 Right to Left.

As I'm at it I'm queering this error also. IOfinSICB.asm(266) : error A2024: invalid operand size for instruction

            Mov Esi, pFfin2              ; Origen dat
            Mov Edi, pMemory
            Mov Ebx, 7
          LoopDeCmp:
       248  Bt TabDeComp, Ebx
            Jnc DorQ
            Dec Ebx
       251  Bt TabDeComp, Ebx
            Jc PassBump                   ; Es Dup
            Fldz                          ; pongo cero
            Jmp PassBump
          DorQ:
            Dec Ebx
       257  Bt [TabDeComp], Ebx
            Jnc esQW
            Fild DWord Ptr [Esi]
            Add Esi, 4
            Jmp PassBump
          esQW:
            Fild QWord Ptr [Esi]
            Add Esi, 8
          PassBump:
       266  Fist QWord Ptr [Edi]
            Add Edi, 8
            Bt Ebx, 2               ; Test 7
            Jnc LoopDeCmp           ; 3 o 1
            Bt Ebx, 1
            Jnc LoopDeCmp           ; 5
            Add Ebx, 8
            Cmp Ebx, 450
            Jl LoopDeCmp

I'm a bit confused with the answer. In the Art of Assembly I found

QUOTE:

6.6.4.2 The Bit Test Instructions: BT, BTS, BTR, and BTC

On an 80386 or later processor, you can use the bt instruction (bit test) to test a single bit. Its second operand specifies the bit index into the first operand. Bt copies the addressed bit into the carry flag. For example, the instruction bt ax, 12 copies bit twelve of ax into the carry flag.

The bt/bts/btr/btc instructions only deal with 16 or 32 bit operands. This is not a limitation of the instruction. After all, if you want to test bit three of the al register, you can just as easily test bit three of the ax register. On the other hand, if the index is larger than the size of a register operand, the result is undefined.

If the first operand is a memory location, the bt instruction tests the bit at the given offset in memory, regardless the value of the index. For example, if bx contains 65 then bt TestMe, bx will copy bit one of location TestMe+8 into the carry flag. Once again, the size of the operand does not matter. For all intents and purposes, the memory operand is a byte and you can test any bit after that byte with an appropriate index. The actual bit bt tests is at bit position index mod 8 and at memory offset effective address + index/8.

The bts, btr, and btc instructions also copy the addressed bit into the carry flag. However, these instructions also set, reset (clear), or complement (invert) the bit in the first operand after copying it to the carry flag. This provides test and set, test and clear, and test and invert operations necessary for some concurrent algorithms.

The bt, bts, btr, and btc instructions do not affect any flags other than the carry flag.

UNQUOTE

It would seem that what I'm doing is correct?

Tyler Tyler · Accepted Answer · 2014-03-11T21:19:56

At 248 and 251 I think your problem is that you forgot the dword []. As is, TabDeComp, without the dword [], is basically an immediate value.

At 257, my only idea is that you need to use dword in front of [TabDeComp]. IIRC, some assemblers require the size specifier. Other than that, it looks correct.

I tested the above with FASM this time to make sure it at least assembled.

At 266, fist stores and dword and you're trying to store it to a qword. So just change qword to dword.

BT invalid instruction operands

2 Answers