Generic clock divider in VHDL

Question

I want to write in VHDL a general clock divider like this:

entity Generic_Clk_Divider is
     Generic(
            INPUT_FREQ: integer := 100;
            OUTPUT_FREQ: integer  := 25;
             );
      Port (
             Clk: in std_logic;
             Rst: in std_logic; 
             Generated_Clk: out std_logic
           );
end entity;

architecture Behavioral of Generic_Clk_Divider is

signal Cnt: integer := 0;
signal Gen_Clk : std_logic := '0';
constant MaxCnt: integer := (integer (INPUT_FREQ/OUTPUT_FREQ)) - 1;


begin 

    process(clk, Rst)
    begin 
        if (Rst = '1') then
            Cnt <= 0;
        elsif rising_edge(Clk) then 
            Cnt <= Cnt + 1 ;
            if (Cnt = MaxCnt) then 
                Gen_Clk <= not Gen_Clk;
                Cnt <= 0;
            end if;
        end if;
     Generated_Clk <= Gen_Clk;
    end process;
end architecture;

It works if I test it with a test bench but it is not working if I use the generated Clk singal with another component (VGA controller in this case) if I but it on a board. My question is about that division between 2 integers, th board seems not to recognize it.

...it is not working if I use the generated Clk signal with another component (VGA controller in this case) if I but it on a board. Can you be a bit more specific? What warnings did you receive during synthesis? How do you determine it's not working? Also note counting 0, 1, 2, 3 then inverting Gen_Clk would give Gen_Clk clock period that's 8 100 MHz clocks or 12.5 MHz. Depending on the device you may have clock resources that will deliver a divide by 4 clock built-in. — user1155120

Tricky Tricky · Accepted Answer · 2019-12-13T10:14:09

Integer/ Integer, returns an integer, with the remainder discarded. So for situations where INPUT/OUTPUT are integer multiples of each other, this is fine. But otherwise, it won't work.

eg.

200/75 = 2
150/40 = 3

etc.

The only way this is really going to work is with real types so you can find the fractional relationships, and then use a much larger counter value to get exact relationships.

But, this isnt really going to help at all, as clock dividers like this are highly discouraged. Logic generated clocks make timing analysis difficult and cause timing problems. It is much safer to use a real clock and generate clock enables instead.

Generic clock divider in VHDL

1 Answers