RISCV RV32IM: MULHSU - which operand is the signed one?

Question

Question

In the risc-v RV32IM, for instruction MULHSU, which one of operands rs1 and rs2 is the signed operand?

Background

The RISC-V Instruction Set Manual Volume I: Unprivileged ISA Document Version 20190608-Base-Ratified say the following (near bottom page 43):

MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2 × XLEN-bit product, for signed × signed, unsigned × unsigned, and signed rs1 × unsigned rs2 multiplication, respectively.

So this states that the signed operand is rs1. But the explicatory note (bottom page 43) say:

MULHSU is used in multi-word signed multiplication to multiply the most-significant word of the multiplier (which contains the sign bit) with the less-significant words of the multiplicand (which are unsigned).

From the definition of the instruction (also page 43):

 31    25 24      20 19         15 14          12 11  7 6      0
+--------+----------+-------------+--------------+-----+--------+
| funct7 | rs2      | rs1         | funct3       | rd  | opcode |
+--------+----------+-------------+--------------+-----+--------+
  7        5          5             3              5     7
  MULDIV   multiplier multiplicand  MUL/MUL[[S]U]  dest  OP

I see that the multiplier is rs2. So the explicatory note states that the signed operand is rs2.

have you tried it on an sifive product to see what their implementation is and/or look at the foundation source code to see their implementation. from what you posted it does appear like a documentation bug, another approach would be to just ask the risc-v foundation folks, I assume there is a forum — old_timer
I think you've just found a documentation issue. You should report it on the official github instead. There's the clarify which operand is signed vs unsigned for mulhsu issue to fix the main text but probably they forgot to fix the footer — phuclv

Alexander Mays Alexander Mays · Accepted Answer · 2019-12-08T17:04:11

I believe either the diagram or "explicatory note" has a typo. All of my testing has shown rs1 to be signed and rs2 to be unsigned for MULHSU.

A much more comprehensive summary of instruction formats & pseudo-codes can be found here. More detail of pseudo-instructions and other things to help write assembly code for RISC-V can be found here (same website). Its documentation specifically expresses MULHSU as follows :

MULHSU rd, rs1, rs2     #rd ← (sx(rs1) × ux(rs2)) » xlen

where sx(r) means signed version, and ux(r) means unsigned version.

If you find any evidence that this isn't the case, please let me know.

RISCV RV32IM: MULHSU - which operand is the signed one?

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