How to split an UInt() into a Vec of UInt to do subword extraction and assignment?

Question

I have a 16bits register declared like that :

val counterReg = RegInit(0.U(16.W))

And I want to do indexed dibit assignment on module output like that :

//..
  val io = IO(new Bundle {
     val dibit = Output(UInt(2.W))
  })
//..
var indexReg = RegInit(0.U(4.W))
//..
io.dibit = vectorizedCounter(indexReg)

But I have some difficulties to know how to declare vectorizedCounter().

I found some examples using Bundles, but for Vector I don't know. And I can't manage to do that with UInt():

val counterReg = RegInit(UInt(16.W))
//...
io.dibit := counterReg(indexReg*2.U + 1.U, indexReg*2.U)

Answer 1

You could dynamically shift and bit extract the result:

io.dibit := (counterReg >> indexReg)(1, 0)