The MMU needs to be told how the OS wants it to translate virtual addresses into physical addresses (and often, when not to translate at all - e.g. if the page at a virtual address needs to be fetched from disk, or if an access to a page should be treated as a programmer error - e.g. dereferencing a NULL pointer).
To do this, the OS provides page tables, and the MMU uses the page tables to translate virtual addresses into physical addresses for the OS.
Essentially, the OS and MMU share the page tables (and the MMU doesn't have its own).
Note that the MMU may cache translations (e.g. TLB entries) to improve performance, but a (limited size) cache isn't the same as the complete original table/s. There are also some (less common) architectures where the MMU only has a cache and doesn't use page tables at all (and when there's a "TLB miss" the CPU/MMU asks the OS to figure out what the translation should be), which is more flexible (the OS can use whatever it likes for page tables because it doesn't have to match what the MMU expects) but slower (higher TLB miss costs).
