Disabling SPI peripheral on STM32H7 between two transmissions?

Question

I'm still doing SPI experiments between two Nucleo STM32H743 boards.

I've configured SPI in Full-Duplex mode, with CRC enabled, with a SPI frequency of 25MHz (so Slave can transmit without issue).

DSIZE is 8 bits and FIFO threshold is 4.

On Master side, I'm sending 4 bytes then wait for 5 bytes from the Slave. I know I could use half-duplex or simplex mode but I want to understand what's going on in full-duplex mode.

volatile unsigned long *CR1 = (unsigned long *)0x40013000;
volatile unsigned long *CR2 = (unsigned long *)0x40013004;
volatile unsigned long *TXDR = (unsigned long *)0x40013020;
volatile unsigned long *RXDR = (unsigned long *)0x40013030;
volatile unsigned long *SR = (unsigned long *)0x40013014;
volatile unsigned long *IFCR = (unsigned long *)0x40013018;
volatile unsigned long *TXCRC = (unsigned long *)0x40013044;
volatile unsigned long *RXCRC = (unsigned long *)0x40013048;
volatile unsigned long *CFG2 = (unsigned long *)0x4001300C;

unsigned long SPI_TransmitCommandFullDuplex(uint32_t Data)
{
    // size of transfer (TSIZE)
    *CR2 = 4;

    /* Enable SPI peripheral */
    *CR1 |= SPI_CR1_SPE;

    /* Master transfer start */
    *CR1 |= SPI_CR1_CSTART;

    *TXDR = Data;

    while ( ((*SR) & SPI_FLAG_EOT)  == 0 );

    // clear flags
    *IFCR = 0xFFFFFFFF;

    // disable SPI
    *CR1 &= ~SPI_CR1_SPE;

    return 0;
}

void SPI_ReceiveResponseFullDuplex(uint8_t *pData)
{
    unsigned long temp;

    // size of transfer (TSIZE)
    *CR2 = 5;

    /* Enable SPI peripheral */
    *CR1 |= SPI_CR1_SPE;

    /* Master transfer start */
    *CR1 |= SPI_CR1_CSTART;

    *TXDR = 0;
    *((volatile uint8_t *)TXDR) = 0;

    while ( ((*SR) & SPI_FLAG_EOT)  == 0 );

    *((uint32_t *)pData) = *RXDR;
    *((uint8_t *)(pData+4)) = *((volatile uint8_t *)RXDR);

    // clear flags
    *IFCR = 0xFFFFFFFF;

    // disable SPI
    *CR1 &= ~SPI_CR1_SPE;

    return temp;
}

This is working fine (both functions are just called in sequence in the main).

Then I tried to remove the SPI disabling between the two steps (ie. I don't clear and set again the bit SPE) and I got stuck in function SPI_ReceiveResponseFullDuplex in the while.

Is it necessary to disable SPI between two transmissions or did I make a mistake in the configuration ?

The behaviour of SPE bit is not very clear in the reference manual. For example is it written clearly that, in half-duplex mode, the SPI has to be disabled to change the direction of communication. But nothing in fuill-duplex mode (or I missed it).

followed Monica to Codidact followed Monica to Codidact · Accepted Answer · 2019-09-13T14:04:08

This errata item might be relevant here.

Master data transfer stall at system clock much faster than SCK

Description

With the system clock (spi_pclk) substantially faster than SCK (spi_ker_ck divided by a prescaler), SPI/I2S master data transfer can stall upon setting the CSTART bit within one SCK cycle after the EOT event (EOT flag raise) signaling the end of the previous transfer.

Workaround

Apply one of the following measures:

• Disable then enable SPI/I2S after each EOT event.

• Upon EOT event, wait for at least one SCK cycle before setting CSTART.

• Prevent EOT events from occurring, by setting transfer size to undefined (TSIZE = 0) and by triggering transmission exclusively by TXFIFO writes.

Your SCK frequency is 25 MHz, the system clock can be 400 or 480MHz, 16 or 19 times SCK. When you remove the lines clearing and setting SPE, only these lines remain in effect after detecting EOT

*IFCR = 0xFFFFFFFF;
*CR2 = 5;
*CR1 |= SPI_CR1_CSTART;

When this sequence (quite probably) takes less than 16 clock cycles, then there is the problem described above. Looks like someone did a sloppy work again at the SPI clock system. What you did first, clearing and setting SPE is one of the recommended workarounds.

I would just set TSIZE=9 at the start, then write the command and the dummy bytes in one go, it makes no difference in full-duplex mode.

Keep in mind that in full duplex mode, another 4 bytes are received which must be read and discarded before getting the real answer. This was not a problem with your original code, because clearing SPE discards data still in the receive FIFO, but it would become one if the modified code worked, e.g there were some more delay before enabling CSTART again.

Disabling SPI peripheral on STM32H7 between two transmissions?

1 Answers