How to read input stimuli from file in a loop in systemverilog test bench?

Question

I need to verify my hardware design in an automatic way. What I was used to do with VHDL was to:

Create .txt file with random data, more than 200k (in Python).
Through VHDL testbench acquire data, put them as the input of my hardware design, then collect results.
Compare results with those produced by a model written in C/C++/Python etc.

Everything is done by a script, launched in the terminal.

I'd like to do the same thing in system Verilog, but I'm getting some troubles.

A typical line of the input data file (out of 200k) is: 1 00000000000000000000000001110101 00000000000000000000000000001010

This is my code:

initial begin

    fin_pointer= $fopen("../common/divisorInSample.txt","r");
    fout_pointer= $fopen("../common/divisorHWResults.txt","w");

    @(posedge rst_n);
    @(posedge clk);
    while (! $feof(fin_pointer)) begin
      $fscanf(fin_pointer,"%b %b %b\n",usigned,dividend,divisor);
      valid=1;
      @(posedge clk);
      valid=0;
      @(posedge res_ready);
      $fwrite(fout_pointer,"%b %b\n",quotient,reminder);
    end
    $finish;
    $fclose(fin_pointer);
    $fclose(fout_pointer);
end

I tried different formats in the fscanf like "%b%b%b". But I'm always getting the same behavior: Code seems to stop after the first execution of "fwrite", because I can see the right results in the output file. How can I solve this problem? Thanks

You are not reading from 'fin_pointer' you only use it to check end-of-file. Instead you have some weird 's' you are trying to read from. — Oldfart
Sorry, was just a mistake copying the code! Obviously I'm reading from file pointer — Giuseppe Sarda

Oldfart Oldfart · Accepted Answer · 2019-08-10T05:07:49

I have used your code in Vivado 2018.2 and see no problems.

I had to make some changes but I have not touched the core of the file I/O code.

integer fin_pointer,fout_pointer;
reg  usigned;
reg  [31:0] dividend,divisor;

task ee_se;
 begin

    fin_pointer= $fopen("../../../../tbench/se_ee_in.txt","r");
    if (fin_pointer==0)
    begin
       $display("Could not open file '%s' for reading","se_ee_in.txt");
       $stop;     
    end
    fout_pointer= $fopen("../../../../se_ee_out.txt","w");
    if (fout_pointer==0)
    begin
       $display("Could not open file '%s'  for writing","se_ee_out.txt");
       $stop;     
    end

//    @(posedge rst_n);
//    @(posedge clk);
    # 100;
    while (! $feof(fin_pointer)) begin
      $fscanf(fin_pointer,"%b %b %b\n",usigned,dividend,divisor);
//      valid=1;
//      @(posedge clk);
      #100 ; 
//      valid=0;
//      @(posedge res_ready);
      $fwrite(fout_pointer,"%b %b\n",~dividend,~divisor);
    end
    $finish;
    $fclose(fin_pointer);
    $fclose(fout_pointer);
end
endtask

Input file se_ee_in.txt:

1 00000000000000000000000001110101 00000000000000000000000000001010
0 00000000000000000000000001110111 00000000000000000000000000001111
1 00000000000000000000000001111111 00000000000000000000000000001000

Output file se_ee_out.txt:

11111111111111111111111110001010 11111111111111111111111111110101
11111111111111111111111110001000 11111111111111111111111111110000
11111111111111111111111110000000 11111111111111111111111111110111

How to read input stimuli from file in a loop in systemverilog test bench?

1 Answers