I was following some examples of adding peripheries to the rocketchip. I used the sifive-blocks as reference.
below is an example from their I2C example (I hope it's ok to post it here)
case object PeripheryI2CKey extends Field[Seq[I2CParams]]
trait HasPeripheryI2C { this: BaseSubsystem =>
val i2cNodes = p(PeripheryI2CKey).map { ps =>
I2C.attach(I2CAttachParams(ps, pbus, ibus.fromAsync)).ioNode.makeSink()
}
}
trait HasPeripheryI2CBundle {
val i2c: Seq[I2CPort]
}
trait HasPeripheryI2CModuleImp extends LazyModuleImp with HasPeripheryI2CBundle {
val outer: HasPeripheryI2C
val i2c = outer.i2cNodes.zipWithIndex.map { case(n,i) => n.makeIO()(ValName(s"i2c_$i")) }
}
I understand the makeIO step which is take a bundle and apply the IO on it, but don't understand the makeSink step. Why do they do this step , isn't makeIO enough ?