What is the reset address for Rocket chip?

Question

In which address does the RV64G processor start on reset? Which scala file should I look into to understand/modify the reset vector address?

I tried to add a simple printf statement for the TopIO in the class Top to monitor the MemIO and generated the emulator. When ready,valid = true, the address (io.mem.req_cmd.bits.addr) printed is 0x8 and the tag is (io.mem.req_cmd.bits.tag) = 0x13. I could locate the instruction fetched (in the 128bits wide io.mem.resp.bits.data) at the address 0x200 in the program rv64ui-p-add.dump

So I assume 0x200 is the starting address for the processor. Is this correct?

(a) If this is correct, I am wondering, how does address=0x8 and tag=0x13 translates to 0x200?

(b) The generated address + tag is 32 bits, where as I expect it to be 64bit (being RV64G architecture). In the Configs.scala MIFAddrBits is set to 26 bits (depends on PAddrBits (32) and CacheBlocOffsetBits(log2Up(64)). Why is these set like this?

(c) The PC address shown at the emulator output in verbose mode is 40 bits, but the registers are 64bits. Why the PC address alone is shown to be only 40 bits? A portion of the emulator output is shown below.

C0:         66 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:         67 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:         68 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:         69 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:         70 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Addr (io.mem.req_cmd.bits.addr) - 0x0000008  :: Tag (io.mem.req_cmd.bits.tag) - 0x13  ::  rw (io.mem.req_cmd.bits.rw)- 0
C0:         71 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:         72 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:         73 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:         74 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:         75 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:         76 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:         77 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:         78 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
...
...
...
C0:         99 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:        100 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x00054863f000257300051063f1002573 :: Tag (io.mem.resp.bits.tag) - 0x13
C0:        101 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x000002975440006f00100e130ff0000f :: Tag (io.mem.resp.bits.tag) - 0x13
C0:        102 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x1f8002931012907300028463de428293 :: Tag (io.mem.resp.bits.tag) - 0x13
C0:        103 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x3412907301428293000002973002b073 :: Tag (io.mem.resp.bits.tag) - 0x13
C0:        104 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:        105 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:        106 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:        107 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:        108 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:        109 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:        110 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:        111 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:        112 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0:        113 [1] pc=[0000000200] W[r10=0000000000000000][1] R[r 0=0000000000000000] R[r16=f4a91906b99f921b] inst=[f1002573] csrr    a0, mhartid
C0:        114 [0] pc=[0000000200] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r16=f4a91906b99f921b] inst=[f1002573] csrr    a0, mhartid
C0:        115 [0] pc=[0000000200] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r16=f4a91906b99f921b] inst=[f1002573] csrr    a0, mhartid
C0:        116 [1] pc=[0000000204] W[r 0=0000000000000000][0] R[r10=0000000000000000] R[r 0=0000000000000000] inst=[00051063] bnez    a0, pc + 0
C0:        117 [1] pc=[0000000208] W[r10=8000000000041129][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f0002573] csrr    a0, mcpuid
C0:        118 [0] pc=[0000000208] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f0002573] csrr    a0, mcpuid
C0:        119 [0] pc=[0000000208] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f0002573] csrr    a0, mcpuid
C0:        120 [1] pc=[000000020c] W[r 0=0000000000000001][0] R[r10=8000000000041129] R[r 0=0000000000000000] inst=[00054863] bltz    a0, pc + 16
C0:        121 [0] pc=[000000020c] W[r 0=0000000000000001][0] R[r10=0000000000000000] R[r 0=f4a91906b99f921b] inst=[00054863] bltz    a0, pc + 16
...
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Answer 1

Quoting the RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.7 (Sec. 3.1.9):

The standard reset vector is either 0xF...FFF00 or 0x0...0200 for high and low locations of the trap vector respectively.

In Rocket this is implemented by setting START_ADDR to 0x200 in src/main/scala/package.scala:

val MTVEC = 0x100
val START_ADDR = MTVEC + 0x100

Answer 2

The privieged architecture is still in draft and this defintion has now changed. See the latest privileged ISA spec

As I write V1.10 is the latest draft. From section '3.3 Resets'

The pc is set to an implementation-defined reset vector.

So implementations can do what they want.

[Incidentally this draft goes on to make the assumption in a paragraph of commentary in section 3.3 that the reset vector differs from the trap base vector (in mtvec). However setting them to the same value is not prohibited in the main text.]