How to split the 8 bit input into two 4 bit data

0
votes

I'm writing a code for QPSK modulation in VHDL. I need to split the 8 bit input data into odd and even bits and each bit is replicated How can i do it.

for example if my input is 11001001 then odd and even bits are odd= 1010 even =1001 my output should be like odd= 11001100 and even is 11000011

1
vhdl
Welcome to Stack Overflow. You're question is not answerable - you have provided no code. You need to write an minimal reproducible example with a clear indication of the step that is giving you trouble. - Matthew Taylor
Your selection/expansion permutations can be done in various ways. Here's one way. Note you haven't provided any information about types nor endian-ness which can affect the definition of even and and odd from left to right. - user1155120

1 Answers

1
votes

Use the concatenation operator '&':

dbl_odds  <=  v(7) & v(7) & v(5) & v(5) & v(3) & v(3) & v(1) & v(1);
dbl_evens <=  v(6) & v(6) & v(4) & v(4) & v(2) & v(2) & v(0) & v(0);