VHDL for 2to1 Multiplexer

Question

This is what I'm trying to write in VHDL code:

I'm still learning so I don't know if what I wrote is correct. Could anyone help me with this multiplexer?

Multiplexer

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE mux2to1_package IS
   COMPONENT mux2to1
        PORT (  s, w0, w1: IN   STD_LOGIC ;
            f       : OUT   STD_LOGIC ) ;
   END COMPONENT ;
END mux2to1_package ;

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY mux2to1 IS
PORT (  s, w0, w1   : IN    STD_LOGIC ;
        f   : OUT   STD_LOGIC ) ;
END mux4to1 ;

ARCHITECTURE Behavior OF mux2to1 IS 
BEGIN
   IF s='0' THEN
      f <= w0;
   ELSE
      f <= w1;
   END IF;
END Behavior ;

Code

ENTITY mux2 IS
PORT (  s, w    : IN    STD_LOGIC ;
    f   : OUT   STD_LOGIC ) ;
END mux2 ;

ARCHITECTURE structure OF mux2 IS   
   SIGNAL m : STD_LOGIC;
BEGIN
   mapping: mux2 PORT MAP ( w(0), w(1), s(0), m(0) ) ;
END Structure ;

I feel like the mapping part is not correct at all.

Port maps contain association lists between formals (signals declared in an entity) and actuals (signals in the design where the entity is being instantiated). Associations can either be named or positional. For positional association in a component instantiation the order must match the component declaration (here likely from the default binding indication, lacking a complete design specification). That does not appear to be the case. IEEE Std 1076-2008 6.5.7 Association lists, 6.5.7.3 Port map aspects. Try this PORT MAP ( s(0), w(0), w(1), m(0)) ; Do you have a specific error? — user1155120
if statements can only be used inside a process (or function/procedure). — Juergen
And you are trying to recursively instantiate mux2 which will not work. — Juergen

Apollo Apollo · Accepted Answer · 2019-05-10T16:20:56

Multiplexer :

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE mux2to1_package IS
   COMPONENT mux2to1
        PORT (  s, w0, w1: IN   STD_LOGIC ;
            f       : OUT   STD_LOGIC ) ;
   END COMPONENT ;
END mux2to1_package ;

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY mux2to1 IS
PORT (  s, w0, w1   : IN    STD_LOGIC ;
        f   : OUT   STD_LOGIC ) ;
END mux2to1;

ARCHITECTURE Behavior OF mux2to1 IS 
BEGIN
  PROCESS(s,w0,w1)
  BEGIN

     IF s='0' THEN
        f <= w0;
     ELSE
        f <= w1;
     END IF;

  END PROCESS;
END Behavior ;

Testbench code :

library ieee;
use ieee.std_logic_1164.all;
use work.mux2to1_package.all;

ENTITY tb IS
END tb;

ARCHITECTURE arch OF tb IS
    SIGNAL s : std_logic := '0';
    SIGNAL w0, w1 : std_logic := '0';
    SIGNAL f : std_logic := '0';
BEGIN
    UUT : ENTITY work.mux2to1 port map(s => s, w0 => w0, w1 => w1, f => f);

    PROCESS
    BEGIN
        s <= 'X';
        w0 <= 'X';
        w1 <= 'X';
        wait for 1 ns;

        s <= '0';
        w0 <= '1';
        w1 <= '0';
        wait for 1 ns;

        s <= '1';
        w0 <= '0';
        w1 <= '1';
        wait for 1 ns;

        s <= '0';
        w0 <= '0';
        w1 <= '1';
        wait for 1 ns;

        assert false report "End of test";
        wait;
    END PROCESS;
END arch;

Like user1155120 mentioned, you weren't careful during signal associations in port map for mapping. In mux2to1 entity you listed s,w0,w1 and f in that order. In port map you used positional association, but you didn't do the association properly. The way user1155120 did it is correct if you want to use positional association. If you want to do it using name association, like I did in code above, it isn't necessary to list the signals in the same order they are listed in entity (listed in the same order in the sense that you are watching out what is done by which signal). When using name association, you can do the following:

UUT : ENTITY work.mux2to1 port map( f => f, w0 => w0, w1 => w1, s => s,);

You can mix up their order.

Also in your Code section, during port mapping, it seems you are trying to use vectors, but they aren't set anywhere before, so you can't really use them.

As Juergen mentioned, you are using if statements without the process, which has been rectified in the code above.

A quick note on using package : when writing testbench like I did, or using that package in any other VHDL design, following line is necessary :

use work.mux2to1_package.all;

Also it is commendable you are using package structure, but at this level, I don't really think it is necessary. You could've simply declared ENTITY.

VHDL for 2to1 Multiplexer

2 Answers