Makefile with Objects in Separate Directory Tree

Question

I have been trying to devise a makefile example which can build object files to a different directory structure than the associated source. The directory tree, both with source and targets, is as follows:

/repo-root
|-- /build
    |-- /example_lib
        |-- makefile
        |-- /Release*
            |-- libexample_lib.a*
            |-- /obj*
                |-- example_lib.o*
                |-- example_lib.d*
|-- /source
    |-- /example_lib
        |-- /inc
            |-- example_lib.h
        |-- /src
            |-- example_lib.cpp

The asterisk folders/files are those the makefile should be generating.

I have seen other questions and answers (Makefile : Build in a separate directory tree), (Makefile with directory for object files), etc., but if I understand their source-to-object rules correctly these appear to create a subdirectory tree within the output directory matching that of the source.

The current makefile I am using is as follows, run using GNU Make 3.82:

SHELL = /bin/sh

.SUFFIXES:
.SUFFIXES: .cpp .o

# @todo Variables passed to make.
BUILD_CONFIG=Release

# Makefile specific variables
REPO_ROOT=../..
LIBRARY_NAME=example_lib

#-------------------------------------------------------------------
# Derived variables
#-------------------------------------------------------------------

LIBRARY_FILENAME=lib$(LIBRARY_NAME).a
LIBRARY_FILEPATH=$(BUILD_CONFIG)/$(LIBRARY_FILENAME)

# Source directories
CPP_SRC_DIRS=$(REPO_ROOT)/source/example_lib/src

# Source files
vpath %.cpp $(CPP_SRC_DIRS)
CPP_SRCS=$(foreach cpp_src_dir, $(CPP_SRC_DIRS), $(wildcard $(cpp_src_dir)/*.cpp))

# Object/dependencies directory
OBJ_DEPS_DIR=./$(BUILD_CONFIG)/obj

# Object files
OBJS=$(CPP_SRCS:%.cpp=$(OBJ_DEPS_DIR)/%.o)

# Dependency files (built with objects)
DEPS=$(CPP_SRCS:%.cpp=$(OBJ_DEPS_DIR)/%.d)

#-------------------------------------------------------------------
# C++ compiler settings
#-------------------------------------------------------------------

CPP_COMMAND=g++
CPP_OPTIONS_INC_PATHS=-I"$(REPO_ROOT)/source/example_lib/inc"
CPP_OPTIONS_OPTIM=-O3
CPP_OPTIONS_WARN=-Wall
CPP_OPTIONS_MISC=-c -fmessage-length=0
CPP_OPTIONS=$(CPP_OPTIONS_INC_PATHS) $(CPP_OPTIONS_OPTIM) $(CPP_OPTIONS_WARN) $(CPP_OPTIONS_MISC)

#-------------------------------------------------------------------
# Archiver settings
#-------------------------------------------------------------------

AR_COMMAND=ar
AR_OPTIONS=-r

#-------------------------------------------------------------------
# Targets
#-------------------------------------------------------------------

# Object/dependency directory target
$(OBJS): | $(OBJ_DEPS_DIR)
$(OBJ_DEPS_DIR):
    mkdir -p $(OBJ_DEPS_DIR)

# Object targets
$(OBJ_DEPS_DIR)/%.o: %.cpp
    @echo 'Building file: $<'
    @echo 'Invoking: GCC C++ Compiler'
    $(CPP_COMMAND) $(CPP_OPTIONS) -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<"
    @echo 'Finished building: $<'
    @echo ' '

# 'all' target
all: $(LIBRARY_FILEPATH)

# Output library target
$(LIBRARY_FILEPATH): $(OBJS)
    @echo 'Building target: $@'
    @echo 'Invoking: GCC Archiver'
    $(AR_COMMAND) $(AR_OPTIONS)  "$@" $(OBJS)
    @echo 'Finished building target: $@'
    @echo ' '

# 'clean' target
clean:
    @echo 'Cleaning targets'
    rm -rf $(OBJS) $(DEPS) $(LIBRARY_FILENAME)
    @echo ' '

# 'PHONY' target
.PHONY: all clean

What 'make' outputs, which makes sense, is:

make all 
Building file: ../../source/example_lib/src/example_lib.cpp
Invoking: GCC C++ Compiler
g++ -I"../../source/example_lib/inc" -O3 -Wall -c -fmessage-length=0 -MMD -MP -MF"Release/obj/../../source/example_lib/src/example_lib.d" -MT"Release/obj/../../source/example_lib/src/example_lib.o" -o "Release/obj/../../source/example_lib/src/example_lib.o" "../../source/example_lib/src/example_lib.cpp"
../../source/example_lib/src/example_lib.cpp:6:1: fatal error: opening dependency file Release/obj/../../source/example_lib/src/example_lib.d: No such file or directory
 }
 ^
compilation terminated.
make: *** [Release/obj/../../source/example_lib/src/example_lib.o] Error 1

The source-to-object rule is substituting the full path of the %.cpp file into the %.o target, which results in an object path of:

Release/obj/../../source/example_lib/src/example_lib.o

What I don't understand is how to get the implicit rules for a source and object file to match when they are in different trees. I used vpath for this to help with source resolution, but the object (target) portion doesn't match up. I also tried changing the source-to-object rule to:

$(OBJ_DEPS_DIR)/$(notdir %.o): %.cpp

But this resulted in the same path (it appears commands like $(notdir ...) aren't supported for wildcard matching?). I also realize that dropping all object files from potentially different source directories could result in a name collision if the two source directories happen to have a file with the same name - this isn't a problem for the code I am working with.

Any help is appreciated, and thanks in advance!

how to get the implicit rules for a source and object file to match when they are in different trees Then you have to write the (pattern) rule for every pair of matching "build-source" (sub-)directories. That process could be automated using make macro facilities. — Matt

Beta Beta · Accepted Answer · 2019-02-21T01:22:03

The trick is to remove the unneeded paths to the source files, before constructing the names of the object files:

CPP_SRCS=$(foreach cpp_src_dir, $(CPP_SRC_DIRS), $(wildcard $(cpp_src_dir)/*.cpp))
# CPP_SRCS now contains "../../source/example_lib/src/example_lib.cpp"
SRCS := $(notdir $(CPP_SRCS))
# SRCS now contains "example_lib.cpp"
BAD_OBJS := $(CPP_SRCS:%.cpp=$(OBJ_DEPS_DIR)/%.o)
# BAD_OBJS now contains "./Release/obj/../../source/example_lib/src/example_lib.o"
OBJS := $(patsubst %.cpp,$(OBJ_DEPS_DIR)/%.o,$(SRCS))
# OBJS now contains "./Release/obj/example_lib.o"

Some small adjustments to your rules are possible, once you have this much working.

Makefile with Objects in Separate Directory Tree

1 Answers