I have a MESI protocol question. Assume that I have two cores (core 1 and 2) and each core has its own l2 cache. When two core has the same data and cache lines are in status S, meaning they both have clean and the same data. At t=0, core 1 writes the cache line and core 1 will switch to M (modified) and core 2 eventually will be in I (invalid) state. In physical world, it takes time for this transaction to finish. Let's say it takes 5 seconds for cache 2 knows that cache 1 updated the cache line.
Assume that at t=2, core 2 writes the same cache line and switch to M status. This write action from core 2 will be notified to the core 1 at t=7 (2+5). Then core 2 needs to invalidates cache 2 at t=5 and core 1 invalidates the line at t=7. Now both lines are invalidated and the data written by the core 1 and then core 2 got lost. This is obviously not following the protocol. What is wrong with my logic and how to prevent this nonsense?
