MESI protocol understanding state transitions

3
votes

In the state transition diagram shown below for the Illinois MESI protocol, why is there a Flush' signal when transitioning from state S to state I and a Flush signal when going from state E to state I upon observing a BusRdX signal. Wouldn't the cache content for processors in these states be the same as the content in main memory? If so, what would be the point of these caches going to state I to flush their data? Also, what exactly is the difference between Flush and Flush'. Is it just that in Flush', data is exchanged transferred by one cache?

Transition diagram:

enter image description here

1
cachingmultiprocessingmesi

1 Answers

1
votes

Wouldn't the cache content for processors in these states be the same as the content in main memory?

This depends on the write policy.

  • If the write-through policy is used and all changes are directly written back to main memory, you are right.

  • But that's not true for write-back. There could be a state transition from M to S through a snoop read (or relating to your diagram: BusRd, i.e. read request from the bus without intent to modify), at this point the cache is not consistent with the main memory, so the content has to be written back to main memory, if the cache is invalidated.

Also, what exactly is the difference between Flush and Flush'

I assume you have the diagram from wikipedia; there is an updated version, I linked to it above, that doesn't make that distinction.