UART Receiving Data in VHDL

Question

I am trying to build a simple UART in VHDL code which receive a character then send back to PC. My program based on this sample code enter link description here. The UART transmission is working normally but with UART reception, it received nothing. After Synthesize is finished, there was some warnings about ff/latch which makes "store" data are constant value.

WARNING:Xst:1293 - FF/Latch <store_2> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <store_3> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <store_4> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <store_5> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <store_6> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <store_7> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <state1_FSM_FFd8> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <state1_FSM_FFd5> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <state1_FSM_FFd7> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <state1_FSM_FFd6> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <state1_FSM_FFd4> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <state1_FSM_FFd3> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.

Please help me and thanks in advance! And here is my basic code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity uart is
port (   clk   : in   std_logic;
         rx    : in   std_logic;
         tx    : out  std_logic);

end uart;

architecture Behavioral of uart is
--fsm for transmission
type fsm  is (idle,b1,b2,b3,b4,b5,b6,b7,b8,b9);                         
signal state  : fsm  := idle;

--fsm for reception
type fsm1 is (idle1,b11,b21,b31,b41,b51,b61,b71,b81,b91);       
signal state1 : fsm1 := idle1;

signal start  : std_logic;
signal store  : std_logic_vector (7 downto 0) := "00000000"; 
--store received data

begin

--reception
process(clk)
variable i : integer := 0;  --baudtick
begin
if clk'event and clk = '1' then 
    i := i + 1;

    if state1 = idle1 then
    start <= rx;
    end if;
    if start = '0' then  --check start bit 0
    state1 <= b11;
    elsif start = '1' then
    state1 <= idle1;
    end if;

    --store 8 bits
    if (state1 = b11) then --1
    store(0) <= rx;
        if i = 26042 then
        state1 <= b21;
        i := 0;
        end if;
    end if;

    if (state1 = b21) then --2
    store(1) <= rx;
        if i = 26042 then
        state1 <= b31;
        i := 0;
        end if;
    end if;

    if (state1 = b31) then --3
    store(2) <= rx;
        if i = 26042 then
        state1 <= b41;
        i := 0;
        end if;
    end if;

    if (state1 = b41) then --4
    store(3) <= rx;
        if i = 26042 then
        state1 <= b51;
        i := 0;
        end if;
    end if;

    if (state1 = b51) then --5
    store(4) <= rx;
        if i = 26042 then
        state1 <= b61;
        i := 0;
        end if;
    end if;

    if (state1 = b61) then --6
    store(5) <= rx;
        if i = 26042 then
        state1 <= b71;
        i := 0;
        end if;
    end if;

    if (state1 = b71) then --7
    store(6) <= rx;
        if i = 26042 then
        state1 <= b81;
        i := 0;
        end if;
    end if;

    if (state1 = b81) then --8
    store(7) <= rx;
        if i = 26042 then
        state1 <= idle1;
        i := 0;
        end if;
    end if;     
  end if;
end process;

--transmission      
process(clk)
variable i : integer := 0;  --baudtick
begin
if clk'event and clk = '1' then 
    i := i + 1;

    if state = idle then
        if start = '0' then  --send start bit 0
        tx <= '0';
            if i = 26042 then
            state <= b1;
            i := 0;
            end if;
        elsif start = '1' then
        state <= idle;
        end if;
    end if;

    --send 8 bits
    if (state = b1) then --1
    tx <= store(0);
        if i = 26042 then
        state <= b2;
        i := 0;
        end if;
    end if;

    if (state = b2) then --2
    tx <= store(1);
        if i = 26042 then
        state <= b3;
        i := 0;
        end if;
    end if;

    if (state = b3) then --3
    tx <= store(2);
        if i = 26042 then
        state <= b4;
        i := 0;
        end if;
    end if;

    if (state = b4) then --4
    tx <= store(3);
        if i = 26042 then
        state <= b5;
        i := 0;
        end if;
    end if;

    if (state = b5) then --5
    tx <= store(4);
        if i = 26042 then
        state <= b6;
        i := 0;
        end if;
    end if;

    if (state = b6) then --6
    tx <= store(5);
        if i = 26042 then
        state <= b7;
        i := 0;
        end if;
    end if;

    if (state = b7) then --7
    tx <= store(6);
        if i = 26042 then
        state <= b8;
        i := 0;
        end if;
    end if;

    if (state = b8) then --8
    tx <= store(7);
        if i = 26042 then
        state <= b9;
        i := 0;
        end if;
    end if;

    if (state = b9) then --stop
    tx <= '1';
        if i = 26042 then
        state <= idle;
        i:= 0;
        end if;
    end if;
 end if;
 end  process;
 end Behavioral;

1/ Your rx seems to come straight from outside. You have to synchronize that first. 2/ The baudrate is rather 'static'. 3/ Try to start using loops to process 8 bit. What if you have a protocol requiring you to receive/transmit 328 bits? — Oldfart

Morten Zilmer Morten Zilmer · Accepted Answer · 2019-01-10T09:03:39

The warning about "FF/Latch trimming" indicates that the synthesis tool has determined that some part of the design, FFs in this case, are unused, thus can be removed. For the specific code it indicates a bug in the design, since all 8 bits of store are required for the design to work correctly.

When making a design for synthesis then you should simulate the code to ensure correct functionality before trying to get the design to work on the hardware (FPGA). Such a simulation of your design will reveal the it is not working as expected. The ModelSim simulator is available for free in the Intel Quartus suite for use on small designs.

You should probably look at the first lines in the receive process:

...
if state1 = idle1 then
    start <= rx;
end if;
if start = '0' then  --check start bit 0
    state1 <= b11;
...

UART Receiving Data in VHDL

1 Answers