0
votes

I am new to make. I tried running sample make as shown below.

CC=gcc
CFLAGS=-I.
OBJ = hellofunc.o hellomake.o
SRC = hellofunc.c hellomake.c
DEPS := $(OBJ:.o=.d)

%.o: %.c
        $(CC) -MT $@ -MMD -MP -MF $(patsubst %,%.d,$(basename $@)) -o $@ -c $(CFLAGS) $<

test:
        @echo "inside test target"

hellomake: hellomake.o hellofunc.o
        $(CC) -o $@ $^


include $(DEPS)

Output :

inside test target

As per make manual, it is saying that By default, make starts with the first target (not targets whose names start with ‘.’). So in this case first target is %.o: %c, right? Why it is not running that rule first? I don't have object files in my directory. make has to check for the absence of object files and try to build with C files using first rule, right?

1
Possible duplicate of What is a 'make target'? - tripleee
A pattern rule doesn't define a target. Just like a template doesn't define a class or a document (depending on what kind of template you are thinking of). A pattern rule says "if you don't have a recipe to build a given target which matches this pattern, here's a way to do it". Since it doesn't refer to a specific target it cannot be used to choose the specific target which is the default goal for make. - MadScientist
@MadScientist Thanks for your explanation. - santosh

1 Answers

0
votes

That's a pattern rule, not a target. It does not specify a specific target file name, just a rule for how to produce an *.o file (to use shell wildcard notation) if there should ever be a circumstance in which you need to do that.

You should probably move the hellomake rule so it comes before test (and probably before the pattern rule, too, for human legibility).

If you want all those $(CC) options to be applied to all *.c files, just add them to CFLAGS. Then there is no need really to override make's built-in pattern rule.