0
votes

So I have a makefile1 that invokes another makefile2 to compile a project. I am setting some C defines in one of my .c files in the project and they are passed in through the GLOBAL_DEFINES make variable(in makefile2), which is expanded to ‘-D…’ when the compiler is invoked. I am passing the values to those C defines as an argument to makefile1 (make param1=XX param2=YY), while this works well but when I do not provide this params and run only make , the compilation fails complaining param1= and param2= are not defined. Any idea how to handle this gracefully.

Here is my actual command that works

make FW_VERSION_MAJOR=33 FW_VERSION_MINOR=4

What I want to achieve here is: I should be able to run make, make param1=XX and make param2=YY successfully.. One approach is to write those #defines to a test file so when I run make without params it gets the value of param1 and param2 from the file and if I apply the params it overwrites them in the file. Is this the best way to handle this ? if Yes, could someone guide me in the right direction.

make --version
GNU Make 3.81
Copyright (C) 2006  Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.

This program built for x86_64-pc-linux-gnu
1
Please provide an actual example of a make invocation you currently use. It cannot be the case that you're running literally make -param1 -param2 and having that work at all. Make does NOT allow you to create your own command line options (preceded by -). It will always parse all options and throw an error if any of them are not valid make command options.MadScientist
@MadScientist I have edited the post with my actual command. Sorry for the confusion.Kalangu
@MadScientist Also, GLOBAL_DEFINES += FW_VERSION_MAJOR=$(FW_VERSION_MAJOR) GLOBAL_DEFINES += FW_VERSION_MINOR=$(FW_VERSION_MINOR) This is what I am doing for the value assignment. The intent is to pass the value of the FW_VERSION_MAJOR and FW_VERSION_MINOR make environment variable (which I should be able to pass on the command line into make) into the compiler as a preprocessor (#define) definition.Kalangu
First you have to decide one basic thing: how do you want to communicate the macro values to the compiler? You have two choices: you can specify them on the compiler command line with -D, or you can write out #define statements to a header file. The former is easier to implement in make. The latter, once you get it set up and working, will likely be more robust (that is, make will be able to rebuild all the files that need to be rebuilt when the values change). The latter also requires changes to your source code, to add #include lines for the new file.MadScientist
@MadScientist Thanks for the help. I finally got it working with the latter approach.Kalangu

1 Answers

0
votes

You could use the conditionnal variable assignation operator (it's a bit hidden in the gnu make doc) in your first Makefile :

FW_VERSION_MAJOR ?= x.x.x

That way if FW_VERSION_MAJOR is not defined (by your command line assignement) it will get a default value and your compilation will proceed.

That has the avantage to not require changes or addition to your source code.