What is the difference between input and reg in Verilog?

0
votes

I have a circuit whose truth value looks like this A =BC+^C[(B and C) or (not C)]

Here I give,

output A;
input B, C;
wire w1, w2;

and (w1, B, C);
not (w2, C);
or (A, w1, w2);

My question is why do we write input B, C; Can we write it as reg B, C;?

What exactly is the difference?.

2
veriloghdl
refer this stackoverflow.com/questions/33459048/… – Mahi
An input can not be a reg. An output can be a reg but not in your case as the and/not/or gates need wires. For the rest see @Mahi 's link. – Oldfart
Possible duplicate of What is the difference between reg and wire in a verilog module – Qiu

2 Answers

0
votes

You are not showing a complete example, but inputs and outputs are part of a hierarchical module declaration. reg is a data type associated with a signal. Typically one encapsulates your circuit in a module, and then you instantiate that module in a top-level module to provide stimulus and observe the outputs. 

module circuit( output wire A;
                input wire B, C;
  wire w1, w2; // internal wires

  and (w1, B, C);
  not (w2, C);
  or (A, w1, w2);
endmodule
module top;
reg B,C; // these are different signals that get connected to the circuit wires
wire A;
circuit c(A,B,C);
initial begin
   B = 0; C = 0;
   ...
endmodule
0
votes

comparing input and reg is similar to comparing a keyboard to a verilog code. input defines a direction of a port. reg defines a data type.

However, every port has a data type associated with it. Default data type for an input/output port is wire. So input B is the same as input wire B.

Now, the right question is: what would be a differnce between wire and reg. wire is a data type for describing connection between module instances. Its main characteristic is that it should always be connected and cannot keep is state otherwise. reg can keep the state if not connected. There are multiple differences in usage which you can find in corresponding verilog tutorials.