As I understand the lower part of the kernel memory is 1:1 mapped with physical address (RAM), I wonder what benefit it brings in, especially in context of x86. When MMU/TLB is enabled, every address sent over CPU address bus is treated as a virtual/logical address. Even if the the linear-to-physical translation can be done by subtracting an offset, but the MMU will still walk the page table to translate the linear address. I can't see any performance benefit apparently. What do I miss?
1 Answers
1
votes
There is no benefit.
Protect Mode provides paging mechanism, so each process can be isolated completely and be protected. When paging is enabled, all address used in code (kernel or user program) must be virtual address and it's impossible to use physical address directly. Kernel just needs a simple method to access every byte in RAM. Under paging mechanism, the simplest mapping schema is 1:1 mapping. Although kernel still can't skip the page mapping process, this schema is very simple to implement. Any other complex mapping schema won't have obvious benefits.
