Chisel code showing wrong output

Question

This is the code for byte selector

class Comp extends Module {
val io = IO(new Bundle {
val in = Input(UInt(25.W))
val out = Output(UInt(25.W))
val i = Input(UInt(4.W))
val out0   = Output(UInt(5.W))
val out1   = Output(UInt(5.W))

})


val r8 = Wire(UInt(5.W))
io.out := Reverse(io.in)
for (i <- 0 to 20 by 5)

{

io.out0 := io.out (i+4, i)


when(io.out0 === 31.U) {
r8 := 0.U            
}.elsewhen(io.out0 === 0.U) {
    r8 := 31.U
}.elsewhen(io.out0 === 17.U) {
    r8 := 14.U  
}.elsewhen(io.out0 === 14.U) {
    r8 := 17.U            
}.otherwise {
    r8 := 27.U            
}


io.out1 := r8
}

This only selects the byte 20 to 24 i.e. when i = 20 and not the rest of the bytes. Everytime I get the output as 27 which is when the for loop selects the most significant 5 bits. Can somebody help?

Can you edit your code adding the declaration of io.out0 signal please ? — FabienM
Ok, according to your full code, it's normal that only bytes 20 to 24 is selected. — FabienM
Yes, but I want it to select 5 different bytes everytime. I can write it using when but that will make the code too long. Is it possible to shorten it with the for loop? — Rahul

FabienM FabienM · Accepted Answer · 2018-07-09T08:57:00

The scala for loop is like GENERATE in VHDL, you have to see it as a multiple declaration of :

io.out0 := io.out (i+4, i)

You can see it as following code :

io.out0 := io.out (4, 0)
io.out0 := io.out (8, 5)
io.out0 := io.out (14, 10)
io.out0 := io.out (18, 15)
io.out0 := io.out (24, 20)

The symbol ':=' is a connection between signal. Each line of above code is seen as new connection erasing the old connection.

Then only the last connection will be really used.

To do the connections as you want, you have to change (I think) the declaration of io.out and use an index like following:

for ( i <- 0 to 20 by 5)
{
io.out(i) := io.out (i+4, i)
}

With io.out declared as a Vector (Vec())

Chisel code showing wrong output

1 Answers