SystemVerilog: convert two 1D array into 2D array

0
votes
logic [7:0] a;
logic [7:0] b;
logic [1:0][7:0] c;
assign c = {{a},{b}};

If I had a and b, how could I convert it into type of c? I guess one obvious way is to use:

assign c[0] = a;
assign c[1] = b;

But imagine c was not a logic variable, but a input port of a module.

mymodule inst_mymodule (
    .c_i({{a},{b}}) // c is logic [1:0][7:0]
    .o(out)
);

what would you do?

1
system-verilog

1 Answers

1
votes

Since you are using packed arrays, it does not matter what the type of c is. It just needs to be 16 bits. Also you don’t need the extra {}’s around a and b. You can write {a,b}