Faulty outputs for JK flip flop state diagram implementation

Question

I am trying to implement a simple FSM of JK flip flop in verilog. However I see that the outputs 'q' and 'q_not' are wrong for multiple time instants. I am presenting the code and the output below. Could some one please let me know what's wrong with the code. Especially I would like to know what's wrong with this implementation even though there are other ways to implement JK flip flops.

modules of JK flip flop and testbench

`timescale 1ns/100ps

module jk_ff(j, k, clk, reset, q, q_not);

input j, k, clk, reset;

output reg q, q_not;

reg present_state, next_state;

parameter state_a = 1'b0;
parameter state_b = 1'b1;

always @ (present_state or j or k)
begin:comb_logic

 next_state = state_a;
 //next_state = 0;

 case(present_state)

  state_a: begin
   if (j == 1'b0 && k == 1'b0) begin
     next_state = state_a;
     end
   else if (j == 1'b0 && k == 1'b1) begin
     next_state = state_a;
     end
   else if (j == 1'b1 && k == 1'b0) begin
     next_state = state_b;
     end
   else if (j == 1'b1 && k == 1'b1) begin
     next_state = state_b;
     end
   end

  state_b: begin
   if (j == 1'b0 && k == 1'b0) begin
     next_state =  state_b;
   end
   else if (j == 1'b0 && k == 1'b1) begin
     next_state = state_a;
   end
   else if (j == 1'b1 && k == 1'b0) begin
     next_state = state_b;
   end
   else if (j == 1'b1 && k == 1'b1) begin
     next_state = state_a;
   end
  end
  default: next_state = state_a;
 endcase 
end

always @ (posedge clk or reset)
begin: seq_logic

if (reset) begin
 q <= 1'b0;
 q_not <= 1'b1;
 present_state <= state_a;
 end
 else begin
 present_state <= next_state;

 case(present_state)

   state_a: begin
    q <= 1'b0;
    q_not <= 1'b1;
   end
   state_b: begin
    q <= 1'b1;
    q_not <= 1'b0;
   end
   default: present_state <= state_a;

  endcase
  end
 end

endmodule

//testbench

module jk_ff_tb;

reg j, k, clk, reset;

wire q, q_not;

jk_ff DUT(.j(j), .k(k), .clk(clk), .reset(reset), .q(q), .q_not(q_not));

initial begin
clk =0;
forever #5 clk = !clk;
end

initial begin
 $monitor("j = %b, k = %b, q = %b, q_not = %b", j, k, q, q_not);
 $dumpfile("jk_ff_wave.vcd");
 $dumpvars;
 reset = 1;
 j=1'b0;
 k=1'b1;
#10 reset = 0;

 #15 j=1'b1;
 #15 k=1'b0;
 #15 j=1'b0;
 #15 k=1'b1;
 #15 j=1'b1;
 #15 k=1'b1;


 #10 $finish;  

end

endmodule

output of the test bench simulation showing values of inputs and primary outputs

j = 0, k = 1, reset = 1, q = 0, q_not = 1
j = 0, k = 1, reset = 0, q = 0, q_not = 1
j = 1, k = 1, reset = 0, q = 0, q_not = 1
j = 1, k = 1, reset = 0, q = 1, q_not = 0
j = 1, k = 0, reset = 0, q = 1, q_not = 0
j = 1, k = 0, reset = 0, q = 0, q_not = 1
j = 0, k = 0, reset = 0, q = 1, q_not = 0
j = 0, k = 1, reset = 0, q = 1, q_not = 0
j = 1, k = 1, reset = 0, q = 0, q_not = 1
j = 1, k = 1, reset = 0, q = 1, q_not = 0
j = 1, k = 1, reset = 0, q = 0, q_not = 1

enter code here

Thank you!

EML EML · Accepted Answer · 2018-07-02T08:07:10

You've got all sorts of problems here:

In seq_logic, you assign present_state with a blocking assignment, and the next statement is case(present_state). This tests the old value of present_state, which isn't what you want
Your 'comb_logic' process is sensitive to present_state, but your seq_logic process changes present_state on rising clock edges. At first sight, that seems the right thing to do, but it's not - draw it out. The way you've written this, comb_logic should be sensitive to only J and K

Those two are enough to get the right result, but this is far too complicated for a JK - start again, put everything in one clocked process, dump the next logic process, just use the behaviour of a JK - load, set, or toggle. You should also add the current time to your $monitor.

Faulty outputs for JK flip flop state diagram implementation

1 Answers