For SPI communication on the STM32F407-Discovery board, what is the implication of setting the software slave management bit?

1
votes

I'm learning embedded development, and I'm trying to communicate with the accelerometer (LIS3DSH) on the discovery board using the SPI protocol. I'm only using CMSIS headers so that I'm forced to interact directly with the registers.

According to the schematics, these are the pins being used by the board for communication with the accelerometer:

  • PA5: SPI1_SCK
  • PA7: SPI1_MOSI
  • PA6: SPI1_MISO
  • PE3: CS_I2C/SPI

From my theoretical understanding of the SPI protocol, whenever I want to receive or transmit data between the master and the slave, I first need to pull the CS pin (PE3) down and then start the communication. This seems to be confirmed by the LIS3DSH user manual as well.

But now I'm confused about what the meaning of SSM is. According to the board's user manual, this is what the software slave management bit does:

When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.

The NSS pin is nothing but the slave select pin, right? Which means it is PE3 in this case.

The SSI bit is bit 8 on the SPI_CR1 register. Does this mean I should instead toggle this SSI bit instead of PE3? That doesn't make sense because how would board know that the PE3 is the relevant CS pin?

So how are the CS pin/line and the SSM bit related, if at all?

If they're not related, do I need to configure the PE3 pin with alternate function mode and and as a pull-up, and then pull it low every time I need to communicate using SPI with the accelerometer?

1
embeddedstm32

1 Answers

3
votes

The NSS pin is an input used as a CS by some other device when the SPI peripheral is in slave mode, or can be used as an output to support multi-master configurations.

If you are operating the SPI in single-master mode, the pin is not used at all.

Moreover SPI1_NSS is an alternate function of PA4 or PA15 so not related to the CS GPIO on PE3 in your case. In master mode, any number of available GPIO pins may be used as CS lines for each peripheral on the same SPI bus, and is driven in software - it is not an "alternate function", and not part of, or controlled by, the SPI peripheral.