When using the SPI protocol, is the output data rate synonymous with the baud rate?

0
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I'm trying to learn how the SPI protocol works, and I'm working on a basic project using the STM32F407G-Discovery board.

This board has a built-in accelerometer (LIS3DSH), and it uses the SPI protocol. In the user manual, it states the following:

The LIS3DSH has ±2g/±4g/±6g/±8g/±16g dynamically selectable full-scale and it is capable of measuring acceleration with an output data rate of 3.125 Hz to 1.6 kHz.

This accelerometer is using SPI1, which is connected to APB2. I'm using STM32CubeMX to generate the initialization code (including the clock configuration), and it looks like the APB2 peripheral clock has a default value of 84 Mhz.

Does this mean that I need to configure the APB2 peripheral clock to have such a value that it falls between the range of 3.125 Hz and 1.6 kHz? I can't imagine this is true because I can't get the value low enough in STM32CubeMX since it throws an error if I go too low.

I'm also accounting for the baud rate control SPI register, which allows you to go as low as f-PCLK/256.

In other words, I'm a bit stuck on which clock frequency to use and which baud rate control to use.

I'm still learning embedded programming, and so my terminology might be incorrect.

2
embeddedstm32
Please note that the LIS parts tend to have rather weird and non-standard "SPI". You might have to do various tricks to get them working, check the "SPI" timing parts of the datasheet. - Lundin
There isn’t particularly a standard SPI protocol. SPI is an interface of, from the master: device select line(s), clock, Master output (MOSI) and then the slaves all have their output wired to MISO. Non-addressed slaves have high impedance output. When a slave is selected by its slave select (usually low), it can enable it’s MISO line. Then data is clock simultaneously out of the master on MOSI and the slaves on MISO, eight bits at a time. Each SPI peripheral defines (in its datasheet) the bytewise protocol it follows, and the software in the master implements that protocol. - balmy

2 Answers

2
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the two are not related. the max SPI clock rate is 10Mhz (page 14). The out rate of 3.125Hz to 1.6Khz is how fast the chip does an acceleration conversion. At 3.125Hz, a new conversion result is ready every 320ms, and at 1.6Khz, they are available every 625us. There is a trade off between conversion rates, power consumption and accuracy. The data sheet leaves a lot of holes, I would suggest reading the MMA7660 data sheet to get a better understanding of how these types of chips work and then revert back to your datasheet for implementation details.

0
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You could use the SPI clock frequency with up to 10MHz to get data from this chip. (So a prescaler of 16 and the full rate (84MHz) APB2 clock would be ok)

The SPI clock determines how fast the data is transferred from the chip to the controller not how fast the chip generated new results.

To always get the newest data you could use the IRQ lines from the chip or use an timer to trigger the transmission corresponding to sampling rate.