How to fix Xilinx Xst 1710 warning

Question

I am having this warning in verilog code when i try to synthesize it on xilinx 14.3. They are arising from this part of code:

module Output_calc_debug(
 input clk,
input wire signed [0:7]oc_in,
input [0:2]pid,
output reg signed[0:31]oc_out_1d);
/***code***/
    reg signed[0:1]  L,W,S;  //lines name from output calculator
                    parameter N=2'd0, E=2'd3;
    if(pid==3'd0) // if port=0(North) then this port only can send data to other ports
            begin
            W<=2'd0; S<=2'd1; L<=2'd2; //assigning indecies to assosiated port directions
            end
            else if(pid==3'd1)
            begin
                  S<=2'd1; L<=2'd2;W<=-2'd1;
            end
            else if(pid==3'd2)
            begin
                 W<=2'd1; L<=2'd2;S<=-2'd1;
            end
            else if(pid==3'd3)
            begin
                 W<=2'd1; S<=2'd2;L<=-2'd1;
            end
            else if(pid==3'd4)
            begin
                  W<=2'd1; S<=2'd2; L<=2'd3;
            end
            else
            begin
            W<=-2'd1;L<=-2'd1;S<=-2'd1;
            end
/**code***/

Code for instantiating this module in another module named Port_Debug:

module Port_Debug(
output signed [0:31]oc_out_1d 
,input wire signed [0:31]sc_in_1d 
,input wire signed[0:7]main_in
,output wire signed[0:7]main_out 
,input clk,input [0:2]pid 
);

wire  signed[0:7]inport_out1; 

inport_debug i1(clk,main_in,inport_out1); 
Output_calc_debug oc1(clk,inport_out1,pid,oc_out_1d);  //module output_calc object in port
Scheduler_Debug s1(clk,sc_in_1d,main_out); 

endmodule

Note: This module Port_Debug is instantiated five times in another module

The Warnings says:

WARNING:Xst:1710 - FF/Latch <L_1> (without init value) has a constant value of 0 in block <oc1>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1710 - FF/Latch <L_0> (without init value) has a constant value of 1 in block <oc1>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1710 - FF/Latch <L_1> (without init value) has a constant value of 0 in block <oc1>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1710 - FF/Latch <L_0> (without init value) has a constant value of 1 in block <oc1>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1710 - FF/Latch <L_1> (without init value) has a constant value of 0 in block <oc1>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1710 - FF/Latch <L_0> (without init value) has a constant value of 1 in block <oc1>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1710 - FF/Latch <L_1> (without init value) has a constant value of 1 in block <oc1>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1710 - FF/Latch <W_0> (without init value) has a constant value of 0 in block <oc1>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1710 - FF/Latch <L_1> (without init value) has a constant value of 1 in block <oc1>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1710 - FF/Latch <W_0> (without init value) has a constant value of 0 in block <oc1>. This FF/Latch will be trimmed during the optimization process.

I have searched on google and other forums ,but there seems to be no possible solution to remove it,people keep suggesting to ignore it, which don't want to.

The errors you've included are refering to registers which don't appear in the code you shown us. Please include all of the code relevant to this error, not just the lines with error messages on them. — user149341

Oldfart Oldfart · Accepted Answer · 2018-04-24T06:53:59

That error can come from much further up your code. e.g. if your pid is constant or can't have all possible values, then the derived values are constant as well.

Also fix you code, indices go from high to low: wire signed[7:0] In a byte, LS bit is bit 0 not bit 7.

......Kindly explain...

Example:

wire [1:0] sel;
...
   case(sel)
   2'b00 : examp = 4'h0001;
   2'b01 : examp = 4'h0010;
   2'b10 : examp = 4'h0100;
   2'b11 : examp = 4'h1000;
   endcase

If sel only takes the values 00 and 01 then value will only be 0001 or 0010. In that case value[3] and value[2] will be optimised to zero.

That sel only takes two value can have many causes some of them may be error(s) from your side. The synthesis tool is very clever in that it finds out about these and optimizes all code accordingly.

Ultimate example would be a very big design with one serial output. If the output is not connected (e.g a typing error) the whole design will be optimised away and will end up to be empty.

How to fix Xilinx Xst 1710 warning

1 Answers