Some assembly questions regarding increment, decrement and multiplication

Question

I'm facing some questions since they're not clearly covered in the IA-32 assembly ebook I'm studying:
1-Is the zero bit in status part of EFLAGS register the only bit among status bits affected by "INC" (increment) and "Dec" (decrement) instructions or the parity bit is affected as well?
2-Does mul (unsigned integer multiplication) instruction affect status part of EFLAGS register?

And finally there's a sentence I'm not sure whether I understand clearly:
"the IMUL instruction can be used by both signed and unsigned integers, although you must be careful that the result does not use the most significant bit of the destination. For larger values, the IMUL instruction is only valid for signed integers."
My conception is that when you're going to use this instruction(that has three formats) for unsigned integer multiplication, the operands ought to have a zero in their most significant bit so no use of that bit in this case; and once the intention is to do signed integer multiplication, operands will use the most significant bit naturally as their sign bit, So am I right?

old_timer old_timer · Accepted Answer · 2011-02-12T14:44:42

Many/most instruction set references will tell you which flags are affected by which instructions, this one for example: http://home.comcast.net/~fbui/intel.html

Some reference manuals have that info per instruction, some have a separate table whose purpose is to show what flags are affected and those might not tell you per instruction what flags are affected.

Elsewhere in the documentation you will have to find what the letters mean, most processors refer to Z,V,N,and C. The reference I linked above of course uses different symbols to indicate the flags, so you have to find a table to tell you which flags are which, and then look up the instructions asked in the question.

That covers questions 1 and 2.

For the third question, the understanding will come when you answer the question "what is the difference from a bitwise perspective between signed and unsigned numbers". I find it easiest to think in terms of 2 or 3 bits, knowing that the basic concepts scale up. So for example thinking in terms of 3 bits, how is the bit pattern 0b011 interpreted as an unsigned bit pattern, how is it interpreted as a signed bit pattern? What about 0b111? What about 0b001? And 0b101? And what does a 0b011 times 0b010 give you if done using unsigned numbers? As signed numbers?

If the answer is not apparent yet then write down all 64 combinations of three bit operands, compute the result assuming the numbers are considered unsigned, next to that compute the result with the numbers considered as signed. If you have made no mistakes as the statement in question indicates if the upper bit on either of the operands is set then you wont get the same result between the signed and unsigned math. If the upper bit is clear you will get the same results. The reason comes from understanding the encoding of signed vs unsigned or to use another term, twos complement.

Now try a few interesting 4 bit cases (a few with an upper bit set and a few without) and decide if you get the same results for 4 bit as you did with 3, then perhaps with a calculator try some 8 or 16 bit numbers and decide if the rule applies for any number of bits or if it changes. Then decide if what you learned about 3 bit numbers answers or at least clarifies the statement/question relative to the size of the operands in the IA-32 IMUL instruction.

Some assembly questions regarding increment, decrement and multiplication

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