Verilog testbench for ROM like DUT not working

Question

I'm trying to implement a testbench and write all possible input combinations for my DUT to a file:

module CONTROL_LOGIC_tb();
    // Inputs
    reg [3:0] select_i;
    reg [15:0] addr_i;
    // Output
    wire [7:0] ctrl_o;

    // Instantiate the UUT
    CONTROL_LOGIC UUT(
        .select_i(select_i),
        .ctrl_i(addr_i),
        .ctrl_o(ctrl_o) );

    // Do test
    integer outFile;
    integer idx;

    initial begin
        select_i = 0;
        outFile = $fopen(".\\CTRL.bin", "wb");

        for (idx = 0; idx < 65536; idx = idx +1)
        begin
            addr_i = idx;
            $fwrite(outFile, "%c", ctrl_o);
        end
        $fclose(outFile);
        $finish;
    end
endmodule

Unfortunately the file 'CTRL.bin' is not filled with any useful data. However it's 64kB in size... at least this works!

What am I doing wrong using the variable 'idx' as input for the DUT?

ps: I'm using the Aldec functional Simulation in ispLever (if that matters?).

Matthew Taylor Matthew Taylor · Accepted Answer · 2018-03-27T10:34:35

There is no delay in your for loop:

for (idx = 0; idx < 65536; idx = idx +1)

There must always be some delay between your inputs, otherwise the code generating them just runs in zero time with each new input just overwriting the previous one and no input ever getting applied to the design under test, eg:

for (idx = 0; idx < 65536; idx = idx +1)
    begin
        addr_i = idx;
        #10;
        $fwrite(outFile, "%c", ctrl_o);
    end

Verilog testbench for ROM like DUT not working

1 Answers