I'm trying to understand how to create a C++ testbench to drive stimulus to a DUT in Verilog. Let's say I have a simple scenario:
// Testbench Top.
module tb_top();
import "DPI-C" function void wait_for_input_ready();
initial
wait_for_input_ready();
import "DPI-C" function void notify_input_ready();
always @(posedge clk or negedge rst)
begin
// based on some condition here I want to send input-ready notify.
notify_input_ready();
end
endmodule
And here is my C++ code:
test_case.h
extern "C" void wait_for_input_ready();
extern "C" void notify_input_ready();
test_case.cpp
#include "test_case.h"
std::conditional_variable cond_var;
std::mutex input_mutex;
bool input_ready = false;
void wait_for_input_ready()
{
std::unique_lock<std::mutex> lock(input_mutex);
while(input_ready != true)
cond_var.wait(lock, [&]{return input_ready == true;}); // This is where the problem happens.
}
void notify_input_ready()
{
std::unique_lock<std::mutex> lock(input_mutex);
is_ready = true;
cond_var.notify_one(); // Unblock to wait statement.
}
In this example, the wait statement on the conditional variable blocks forever and does not let the simulator execute any other parts of the Verilog code. So what is the right approach here? Should I create a thread in C++ inside the wait_for_input_ready function and detach it completely?
