Post-increment and Pre-decrement addressing modes on Intel 80386

1
votes

I know how these modes work on other processors, what I don't understand is why doesn´t the 80386 need the post-increment and pre-decrement addressing modes?

Also what´s the relation between these addressing modes and the push and pop instructions?

1
assemblyx86inteladdressing-mode
Do you have a question? If yes, please edit your post to include a question. – fuz
almost no processor needs these modes (at least if it does have indirect addressing and basic arithmetic over general purpose registers). Although they may be handy, but when I'm coding x86 asm, I don't really miss these, one gets used to write the code in other way quickly (but x86 has also lods, stos, movs instructions, etc... so it's not like it lacks post/pre increments completely). – Ped7g
Most RISC machines don't have inc/dec addressing modes. ARM is the exception, being less RISCy than MIPS, SPARC, and so on. – Peter Cordes
Also note that post increment and pre decrement get decoded into the same micro-ops as two separate instructions, so almost no impact on execution speed. – Tim

1 Answers

7
votes

why the 80386 doesn´t need the post-increment and pre-decrement addressing modes?

You never really need post-increment and pre-decrement addressing modes as long as you have ADD/SUB instructions. They're just convenience instructions.

what´s the relation between this addressing modes and the push and pop instructions?

PUSH is pre-decrement save and POP is post-increment load.