Quartus Prime VHDL component instantiation compile error

Question

I am having an issue when trying to compile the following code:

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder_top is
Port ( a_in : in STD_LOGIC_VECTOR (3 downto 0);
       b_in : in STD_LOGIC_VECTOR (3 downto 0);
       clk : in STD_LOGIC;
       clk_en : in STD_LOGIC;
       carry_in : in STD_LOGIC;
       carry_out : out STD_LOGIC;
       c_out : out STD_LOGIC_VECTOR (3 downto 0));
end adder_top;

architecture Behavioral of adder_top is
COMPONENT c_addsub_0
  PORT (
    A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    CLK : IN STD_LOGIC;
    C_IN : IN STD_LOGIC;
    CE : IN STD_LOGIC;
    C_OUT : OUT STD_LOGIC;
    S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
  );
END COMPONENT c_addsub_0;
begin
inst_1 : COMPONENT c_addsub_0
    port map
    (
        A => a_in,
        B => b_in,
        CLK => clk,
        C_IN => carry_in,
        CE => clk_en,
        C_OUT => carry_out,
        S => c_out
    );

end Behavioral;

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---------------------------

I receive the following error code when trying to compile:

Error (12006): Node instance "inst_1" instantiates undefined entity "c_addsub_0". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.

I am entirely unsure why I am receiving this error. Any help would be greatly appreciated.

A little research is in order. If the first question found with an answer (How to define a VHDL component and package?) isn't adequate then your question isn't specific enough. — user1155120

FPGA-guy FPGA-guy · Accepted Answer · 2018-02-26T03:42:22

The synthesis tool (Quartus) used to analyze and elaborate (a.k.a. compile) your design is complaining that it has not found an entity to bind the component c_addsub_0 with. You need to point the tool, in a tool defined way, to a library that contains the desired entity.

If you intended c_addsub_0 to be a block that you created then maybe it did not analyze into the work library as expected (unexpected syntax errors), or the library path to the work library is not established correctly (unlikely for a synthesis tool). If you wrote c_addsub_0 then it may be easier to use direct entity instantiation -- it saves the hassle of writing the component declaration and keep it in sync with the instance and the entity in another file. For example:

inst_1 : ENTITY work.c_addsub_0(<arch_name>)
    port map
    (
        A => a_in,
        B => b_in,
        CLK => clk,
        C_IN => carry_in,
        CE => clk_en,
        C_OUT => carry_out,
        S => c_out
    );

If the c_addsub_0 block is meant to be unbound through elaboration, as a black box until place-and-route, then you need to tell Quartus by decorating the instance with the appropriate syn_black_box attribute.

architecture Behavioral of adder_top is
COMPONENT c_addsub_0
  PORT (
    A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    CLK : IN STD_LOGIC;
    C_IN : IN STD_LOGIC;
    CE : IN STD_LOGIC;
    C_OUT : OUT STD_LOGIC;
    S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
  );
END COMPONENT c_addsub_0;

attribute syn_black_box : boolean;
attribute syn_black_box of c_addsub_0: component is true;

begin
...

It then knows to synthesize a black box representation in the post synthesis netlist for that component. You then need to insure the Quartus back end can find a netlist for the given component in a netlist library path somewhere.

VHDL provides for a variety of ways to create hierarchy with incredibly precise control over binding, signal connections, naming/renaming of blocks and other features which are rarely used in ordinary designs. Unless your synthesis tool only supports one style of instantiation using component declarations or you need a black box, then I would stick with direct entity instantiation.

P.S.: Your use clause use ieee.std_logic_unsigned; should be use synopsys.std_logic_unsigned; -- The IEEE standards body never approved the std_logic_unsigned package. Though, if analyzing with the 1076-2008 standard, it is allowed now to analyze anything you want into the IEEE library. That permits defacto vendor, but not formally standardized, packages to be used without modification of your source code. Only the STD library is now actually a standard. Just be aware that Mentor Graphics and Synopsys versions of this package are different so your code may not achieve the portability that use of the standards based numeric_std package will achieve.

Quartus Prime VHDL component instantiation compile error

1 Answers