generate and propagate signals for 64 bit kogge stone adder using loop in verilog

Question

I am writing a verilog code for 64 bit kogge stone adder. Please help me how to write preprocessing stage of computing generate and propagate signals for 64 bit inputs using loop in verilog?

module preprocessing64bit(a,b,g,p);
input  [63:0] a,b;
output [63:0] g,p;
reg [63:0] g,p;
integer i;

always @ (a or b)
begin
for(i=0;i<64;i=i+1)
begin 
assign p[i]=a[i]^b[i];
assign g[i]=a[i]&b[i];
end
end

endmodule

This code I wrote but is not working. I researched a lot over internet but unable to find the correct way. Error messages being shown on compilation in Modelsim

Error: C:/Users/Ankit/Documents/verilog project/preprocessing64bit.v(11): Bit-select of reg not allowed in procedural continuous assignment: p.

** Error: C:/Users/Ankit/Documents/verilog project/preprocessing64bit.v(12): Bit-select of reg not allowed in procedural continuous assignment: g

Welcome to the site. Please realise that this is not a free design house, homework-answering service or an on-line technical encyclopedia, copied out to you on demand. People will help you take the next step if your question shows that you've done as much as you possibly could on your own - which your post doesn't, I'm afraid. Please revise your question showing your work and findings so far, in considerable detail. Again, a warm welcome to the site. — Oldfart
I made improvements to my question. Thanks for the correction. Please help now. Thanks. — Ankit Mahajan

Oldfart Oldfart · Accepted Answer · 2018-02-03T12:31:00

If you have no experience with Verilog can can understand that the error message has you baffled. Yes, you have made an error, but it has nothing to do whatsoever with the bit-select.

You have used an 'assign' inside an 'always @(...)
'assign' is used with wires and out side 'always' sections.
The correct syntax would be:

   p[i]=a[i]^b[i];
   g[i]=a[i]&b[i];

That will solve your syntax error and the code is then correct.
But let's have another look at your code.....

You are using a for loop to work with bits. But Verilog logical operators will work on vectors. This is much simple and faster:

always @ (a or b)
begin
    p = a ^ b;
    g = a & b ;
end

The next improvement is that you can now also drop the 'always' section and use assigns. But beware an 'assign' work with a 'wire', not a 'reg' thus it becomes:

module preprocessing64bit(a,b,g,p);
input  [63:0] a,b;
output [63:0] g,p;

   assign p = a ^ b;
   assign g = a & b;

endmodule

As last improvement I would not use the old port definitions but use the new Verilog 2001 syntax:

module preprocessing64bit (
 input  [63:0] a,b,
 output [63:0] g,p
 );

generate and propagate signals for 64 bit kogge stone adder using loop in verilog

2 Answers