synthesizable 64 bit full adder in verilog

0
votes

I want to design a synthesizable 64 bit full adder, so I need to instantiate the module 64 times, which makes the code bulky. Can anyone suggest an alternative way to minimize the code?

1
verilog
Use generate to minimize your code. Have a look at this for more details: stackoverflow.com/a/5595254/3951497 – ssgr
Could you explain why your building a 64 bit adder using a 1 bit adder 64 times? – Morgan
Is generate synthesizable? – kartik
@Morgan I wanna design a 64bit full adder. I have created a module for 1bit full adder and calling it in another module. – kartik
@Morgan this approach makes the code very bulky, do you have ways to optimize the code? I want a synthesizable code. – kartik

1 Answers

0
votes

Unless your trying to understand structure of gate level design, using synthesizable RTL is much easier:

localparam WIDTH = 64;
reg [WIDTH-1:0] a;
reg [WIDTH-1:0] b;
reg [WIDTH-1:0] sum;
always @* begin
  sum = a + b;
end


// to make output sync, put through flip flop
reg [WIDTH-1:0] sum_flop;
always @(posedge clk) begin
  sum_flop <= sum;
end

This could be rewritten as the following code but will generate the same hardware.

localparam WIDTH = 64;
reg [WIDTH-1:0] a;
reg [WIDTH-1:0] b;
reg [WIDTH-1:0] sum_flop;

always @(posedge clk) begin
  sum_flop <= a + b;
end